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| www..com SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1783 Advance Information 132 RGB x 160 CSTN LCD Segment / Common COLOR Driver with Controller www..com This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1783 Series Rev 1.4 P 1/79 Jul 2005 Copyright 2003 Solomon Systech Limited www..com www..com 4U www..com TABLE OF CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GENERAL DESCRIPTION ............................................................................................................................5 FEATURES .......................................................................................................................................................5 ORDERING INFORMATION........................................................................................................................5 BLOCK DIAGRAM .........................................................................................................................................6 DIE PAD FLOOR PLAN .................................................................................................................................7 SSD1783U COF PIN ASSIGNMENT (COPPER VIEW) ...........................................................................15 SSD1783U2 COF PIN ASSIGNMENT (COPPER VIEW) .........................................................................16 PIN DESCRIPTION.......................................................................................................................................17 FUNCTIONAL BLOCK DESCRIPTIONS .................................................................................................20 COMMAND TABLE......................................................................................................................................27 COMMAND DESCRIPTIONS .....................................................................................................................37 MAXIMUM RATINGS..................................................................................................................................55 DC CHARACTERISTICS .............................................................................................................................56 AC CHARACTERISTICS .............................................................................................................................57 APPLICATION EXAMPLES .......................................................................................................................70 SSD1783Z DIE TRAY DIMENSIONS..........................................................................................................72 APPENDIX......................................................................................................................................................73 www..com Solomon Systech Jul 2005 P 2/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com TABLE OF TABLES Table 1 - Ordering Information .....................................................................................................................................5 Table 2 - SSD1783 Series Bump Die Pad Coordinates (Bump center) .........................................................................8 Table 3 - Bus interface mode selection by PS2-PS0....................................................................................................17 Table 4 - VOUT > VL5 > VL4 > VL3 > VL2 > VSS Relationship .......................................................................................18 Table 5 - Data bus selection modes .............................................................................................................................21 Table 6 - COMMAND TABLE...................................................................................................................................27 Table 7 - Graphic command table ...............................................................................................................................31 Table 8 - Extended command table .............................................................................................................................33 Table 9 - Read Command Table ..................................................................................................................................35 Table 10 - RAM arrangements of 18-bit/pixel, direct write mode. .............................................................................37 Table 11 - RGB Arrangement modes ..........................................................................................................................39 Table 12 - Data bus arrangement for different pixel and bus mode.............................................................................39 Table 13 - Area scrolling selection modes...................................................................................................................40 Table 14 - Maximum Ratings ......................................................................................................................................55 Table 15 - DC Characteristics......................................................................................................................................56 Table 16 - AC Characteristics......................................................................................................................................57 Table 17 - Parallel Timing Characteristics ..................................................................................................................58 Table 18 - Parallel Timing Characteristics ..................................................................................................................59 Table 19 - Parallel Timing Characteristics ..................................................................................................................62 Table 20 - Parallel Timing Characteristics ..................................................................................................................63 Table 21 - Serial Timing Characteristics .....................................................................................................................66 Table 22 - Serial Timing Characteristics .....................................................................................................................67 Table 23 - Serial Timing Characteristics .....................................................................................................................68 Table 24 - Serial Timing Characteristics .....................................................................................................................69 www..com SSD1783 Series Rev 1.4 P 3/79 Jul 2005 Solomon Systech www..com www..com 4U www..com TABLE OF FIGURES Figure 1 - SSD1783 Block Diagram..............................................................................................................................6 Figure 2 - SSD1783 Die Pad Floor Plan........................................................................................................................7 Figure 3 - Read Display Data ......................................................................................................................................20 Figure 4 - Graphic Display Data RAM Map ...............................................................................................................24 Figure 5 - SSD1783 Booster and Divider Configurations ...........................................................................................25 Figure 6 - Oscillator structural block diagram.............................................................................................................26 Figure 7 - column and page scan direction ..................................................................................................................38 Figure 8 - Area scrolling selection modes ...................................................................................................................41 Figure 9 - GDDRAM updates for area scrolling .........................................................................................................42 Figure 10 - Example of center scroll mode..................................................................................................................43 Figure 11 - Contrast Control Flow Set Segment Re-map ............................................................................................44 Figure 12 - Contrast Control Voltage Range Curve ....................................................................................................45 Figure 13 - Partial display mode..................................................................................................................................46 Figure 14 - OTP programming circuitry......................................................................................................................48 Figure 15 - Flow chart of OTP programming Procedure.............................................................................................49 Figure 16 - 8-bit/16-bit Parallel 6800-series Interface Timing Characteristics............................................................58 Figure 17 - 8-bit/16-bit Parallel 8080-series Interface Timing Characteristics............................................................61 Figure 18 - 8-bit/16-bit Parallel 6800-series Interface Timing Characteristics............................................................62 Figure 19 - 8-bit/16-bit Parallel 8080-series Interface Timing Characteristics............................................................65 Figure 20 - 4 wire Serial Timing Characteristics.........................................................................................................66 Figure 21 - 3 wire Serial Timing Characteristics.........................................................................................................67 Figure 22 - 4 wire Serial Timing Characteristics.........................................................................................................68 Figure 23 - 3 wire Serial Timing Characteristics.........................................................................................................69 Figure 24 - Application example .................................................................................................................................70 Figure 25 - VDD, VDDIO, VCI connection example ........................................................................................................71 Figure 26 - SSD1783Z Die Tray Dimension ...............................................................................................................72 www..com Solomon Systech Jul 2005 P 4/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 1 General Description SSD1783 is a single-chip CMOS color STN LCD driver with controller for dot-matrix graphic liquid crystal display system. SSD1783 consists of 556 high voltage driving output pins for driving maximum 132 RGB Segments, 160 Commons CSTN panel. SSD1783 consists of 132 RGB x 168 x 18 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from common MCU through 16-bit/8-bit 6800-series / 8080-series compatible Parallel Interface or 3-wires / 4-wires Serial Peripheral Interface by pins selection. SSD1783 embeds On-Chip Oscillator, DC-DC Converter, bias divider so as to reduce the number of external component. With the advanced design, low power consumption, stable LCD operating voltage and flexible die package layout, SSD1783 is suitable for any portable battery-driven applications requiring long operation period with compact size. 2 * FEATURES VDDIO = 1.2V - VDD VDD = 2.4V - 3.6V VCI = VDD - 3.6V LCD Driving Output Voltage: 18V max Low Current Sleep Mode Maximum display size: 132 RGB columns by 160 rows. Display color support: 262K/65K/4K/256 color selectable, with preset/programmable color look up table (CLUT) 16-bit/8-bit 6800-series Parallel Interface, 16-bit/8-bit 8080-series Parallel Interface, 3-wires Serial Peripheral Interface and 4-wires Serial Peripheral Interface On-Chip (132 RGB) X (168) x 18 = 399168 bits Graphic Display Data RAM Column Re-mapping and RAM Page scan direction control Center Screen Scrolling, Top Screen Scrolling, Bottom Screen Scrolling and Whole Screen Scrolling 4X / 5X / 6X/ 7X On-Chip DC-DC Converter 64 Levels Internal Contrast Control Programmable LCD Driving Voltage Temperature Compensation Coefficients Programmable drive duty ratio: 1/32 to 1 /160 Non-Volatile Memory (OTP) for calibration On-Chip 2-D Graphic Acceleration Engine featuring Line/Rectangle/Circle Drawing, Dim/Clear/Copy operation in Window mode. FRC or PWM Driving Scheme Interlace/progressive LCD common pins sequence selectable Power Supply: * * * * * * * * * * * * * * * * www..com 3 ORDERING INFORMATION Ordering Part Number SSD1783Z SSD1783U SSD1783U2R1 SEG 132x3 (396) 132x3 (396) 128x3 (384) COM 160 160 160 Package Form Gold Bump Die COF with SMD COF Reference Figure 2 on page 7 Section 15.1 Section 15.2 Remark Table 1 - Ordering Information SSD1783 Series Rev 1.4 P 5/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 4 BLOCK DIAGRAM ROW0 ~ ROW159 COL0 ~COL395 160 Common Driver Circuits 132 RGB Segment Driver Circuits VOUT VL5 VL4 VL3 VL2 VSS Display Data Latch LCD Driving Voltage Generator 4X/ 5X/ 6X/ 7X DC/ DC Converter, Voltage Regulator, Contrast Control Bias Divider Temperature Compensation VCI VCI2x VOUTD3 C4P C2P C2N C1N C1P C1Y C3P BUSY Display SYN Timing M Generator GDDRAM (132RGB) X 168 X 18 bits Page Address Control Circuit Column Address Control Circuit CL www..com Oscillator MPU System Control Circuit 2-D Graphic Accelerator Status Register Command Decoder VDD VDDIO VSS CVSS Microprocessor Interface Logic RVSS LCDVSS CSW H R/ W ( WR ) E ( RD) CS D/ C RES PS0 PS1 PS2 D0 - D15 Figure 1 - SSD1783 Block Diagram Solomon Systech Jul 2005 P 6/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 5 DIE PAD FLOOR PLAN 816 305 centre: (-10500,460) centre: (10500,460) centre: (10500,-460) 279 278 304 817 842 1 centre: (-10500,-460) 25um 25um 25um 25um 75um 18um 25um 25um 25um 25um 25um 25um 25um 25um www..com Die size: 22.10 x 1.96 sq mm Die thickness: 457 +/- 25 um Bump height: 15um (normal) Bump co-planarity: <3um (within die) Note: 1. Diagram showing die face up 2. Coordinates are reference to die centre (in um) 3. All alignment keys do not contain gold bump Bump size: PAD # 1-278 279 280-303 304 305-306 307-814 815-816 817 818-841 842 x (um) 56 118 118 118 50 27 50 118 118 118 y (um) 92 50 27 50 118 118 118 50 27 50 Figure 2 - SSD1783 Die Pad Floor Plan SSD1783 Series Rev 1.4 P 7/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Table 2 - SSD1783 Series Bump Die Pad Coordinates (Bump center) Pad no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal DUMMY DUMMY DUMMY C4P C4P C4P C4P C4P C4P C4P C4P C2P C2P C2P C2P x coor -10842.40 -10491.25 -10414.95 -10338.65 -10262.35 -10186.05 -10109.75 -10033.45 -9957.15 -9880.85 -9804.55 -9728.25 -9651.95 -9575.65 -9499.35 y coor Pad no. -818.00 51 -818.00 52 -818.00 53 -818.00 54 -818.00 55 -818.00 56 -818.00 57 -818.00 58 -818.00 59 -818.00 60 -818.00 61 -818.00 62 -818.00 63 -818.00 64 -818.00 65 Signal NC NC C1Y C1Y C1Y C1Y C1Y C1Y C1Y C1Y C3P C3P C3P C3P C3P x coor -6752.55 -6676.25 -6599.95 -6523.65 -6447.35 -6371.05 -6294.75 -6218.45 -6142.15 -6065.85 -5989.55 -5913.25 -5836.95 -5760.65 -5684.35 y coor Pad no. -818.00 101 -818.00 102 -818.00 103 -818.00 104 -818.00 105 -818.00 106 -818.00 107 -818.00 108 -818.00 109 -818.00 110 -818.00 111 -818.00 112 -818.00 113 -818.00 114 -818.00 115 Signal VOUT VOUT VOUT VOUT VOUT VOUT VOUT NC NC NC NC NC M SYN CL RES x coor -2937.55 -2861.25 -2784.95 -2708.65 -2632.35 -2556.05 -2479.75 -2403.45 -2327.15 -2250.85 -2174.55 -2098.25 -2021.95 -1945.65 -1869.35 y coor -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C2P C2P C2P C2P C2N C2N C2N C2N C2N C2N C2N C2N NC NC NC NC NC C1N C1N C1N C1N C1N C1N C1N C1N C1P C1P C1P C1P C1P C1P C1P C1P -9423.05 -818.00 -9346.75 -818.00 -9270.45 -818.00 -9194.15 -818.00 -9117.85 -818.00 -9041.55 -8965.25 -8888.95 -8812.65 -8736.35 -8660.05 -8583.75 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 C3P C3P C3P NC NC NC NC NC NC -5608.05 -818.00 -5531.75 -818.00 -5455.45 -818.00 -5379.15 -818.00 -5302.85 -818.00 -5226.55 -5150.25 -5073.95 -4997.65 -4921.35 -4845.05 -4768.75 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 -1793.05 -818.00 -1716.75 -818.00 -1640.45 -818.00 -1564.15 -818.00 -1487.85 -818.00 -1411.55 -1335.25 -1258.95 -1182.65 -1106.35 -1030.05 -953.75 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 D/ C D/ C D/ C CS CS VSS PS2 www..com VDD VSS VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VOUTD3 VSS VSS VSS VSS VSS VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PS1 PS0 -4692.45 -818.00 -4616.15 -818.00 -4539.85 -818.00 -4463.55 -818.00 -4387.25 -818.00 -4310.95 -4234.65 -4158.35 -4082.05 -4005.75 -3929.45 -3853.15 -3776.85 -3700.55 -3624.25 -3547.95 -3471.65 -3395.35 -3319.05 -3242.75 -3166.45 -3090.15 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -8507.45 -818.00 -8431.15 -818.00 -8354.85 -818.00 -8278.55 -818.00 -8202.25 -818.00 -8125.95 -8049.65 -7973.35 -7897.05 -7820.75 -7744.45 -7668.15 -7591.85 -7515.55 -7439.25 -7362.95 -7286.65 -7210.35 -7134.05 -7057.75 -6981.45 -6905.15 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 VDD VSS -877.45 -818.00 -801.15 -818.00 R/ W ( WR ) -724.85 -818.00 R/ W ( WR ) -648.55 -818.00 E ( RD ) E ( RD ) -572.25 -818.00 -495.95 -419.65 -343.35 -267.05 -190.75 -114.45 -38.15 38.15 114.45 190.75 267.05 343.35 419.65 495.95 572.25 648.55 724.85 801.15 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 VDD D0 D1 D2 D3 D4 D5 D6 (SCK) D7 (SDA) D8 D9 D10 D11 D12 D13 D14 D15 VSS NC -6828.85 -818.00 -3013.85 -818.00 Solomon Systech Jul 2005 P 8/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Pad no. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 Signal BUSY NC NC NC RVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS LCDVSS 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 x coor 877.45 953.75 1030.05 1106.35 1182.65 1258.95 1335.25 1411.55 1487.85 1564.15 1640.45 1716.75 1793.05 1869.35 1945.65 2021.95 2098.25 2174.55 2250.85 2327.15 2403.45 2479.75 2556.05 2632.35 2708.65 2784.95 2861.25 2937.55 www..com -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 y coor Pad no. Signal x coor y coor Pad no. -818.00 201 251 VDD 4692.45 -818.00 -818.00 202 252 VDD 4768.75 -818.00 -818.00 203 253 VDD 4845.05 -818.00 -818.00 204 254 VDD 4921.35 -818.00 -818.00 205 255 VDD 4997.65 -818.00 -818.00 206 256 VDD 5073.95 -818.00 -818.00 207 257 VDD 5150.25 -818.00 -818.00 208 258 VDD 5226.55 -818.00 -818.00 209 259 VDD 5302.85 -818.00 -818.00 210 260 VDD 5379.15 -818.00 -818.00 211 261 VDD 5455.45 -818.00 -818.00 212 262 VDDIO 5531.75 -818.00 -818.00 213 263 VDDIO 5608.05 -818.00 -818.00 214 264 VCIX2 5684.35 -818.00 265 -818.00 215 VCIX2 5760.65 -818.00 -818.00 216 266 VCIX2 5836.95 -818.00 -818.00 217 267 VCIX2 5913.25 -818.00 -818.00 218 268 VCIX2 5989.55 -818.00 -818.00 219 269 VCIX2 6065.85 -818.00 -818.00 220 270 VCIX2 6142.15 -818.00 -818.00 221 271 VCIX2 6218.45 -818.00 -818.00 222 272 VCIX2 6294.75 -818.00 -818.00 223 NC 6371.05 -818.00 273 6447.35 -818.00 274 -818.00 224 VCI -818.00 225 6523.65 -818.00 275 VCI -818.00 226 6599.95 -818.00 276 VCI -818.00 227 6676.25 -818.00 277 VCI -818.00 228 6752.55 -818.00 278 VCI x coor 8507.45 8583.75 8660.05 8736.35 8812.65 8888.95 8965.25 9041.55 9117.85 9194.15 9270.45 9346.75 9423.05 9499.35 9575.65 9651.95 9728.25 9804.55 9880.85 9957.15 10033.45 10109.75 10186.05 10262.35 NC 10338.65 DUMMY 10414.95 DUMMY 10491.25 DUMMY 10842.40 Signal VL2 VL2 VL2 VL2 VL2 VL3 VL3 VL3 VL3 VL3 VL3 VL4 VL4 VL4 VL4 VL4 VL4 VL4 VL4 VL5 VL5 VL5 VL5 VL5 y coor -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 3013.85 3090.15 3166.45 3242.75 3319.05 3395.35 3471.65 3547.95 3624.25 3700.55 3776.85 3853.15 3929.45 4005.75 4082.05 4158.35 4234.65 4310.95 4387.25 4463.55 4539.85 4616.15 VCI VCI VCI VCI VCI NC NC NC NC NC NC NC NC VSS VSS VSS VSS VSS NC VCIX2 VL3 VL2 6828.85 6905.15 6981.45 7057.75 7134.05 7210.35 7286.65 7362.95 7439.25 7515.55 7591.85 7668.15 7744.45 7820.75 7897.05 7973.35 8049.65 8125.95 8202.25 8278.55 8354.85 8431.15 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 -818.00 SSD1783 Series Rev 1.4 P 9/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Pad no. 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 Name DUMMY ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 DUMMY DUMMY x coor 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10812.40 10846.40 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 DUMMY 10733.20 791.00 ROW24 ROW25 ROW26 ROW27 ROW28 ROW30 ROW31 ROW32 ROW33 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 10679.90 10638.10 10596.30 10554.50 10512.70 10429.10 10387.30 10345.50 10303.70 10220.10 10178.30 10136.50 10094.70 10052.90 10011.10 9969.30 9927.50 9885.70 9843.90 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 www..com 356 ROW73 8631.70 791.00 8589.90 8548.10 8506.30 8464.50 8422.70 390 357 358 359 360 361 362 ROW74 ROW75 ROW76 ROW77 ROW78 791.00 791.00 791.00 791.00 791.00 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 COL368 COL367 SEG122 COL366 COL365 COL364 SEG121 COL363 COL362 COL361 SEG120 COL360 COL359 COL358 SEG119 COL357 COL356 COL355 SEG118 COL354 COL353 COL352 SEG117 COL351 COL350 COL349 SEG116 COL348 COL347 COL346 SEG115 COL345 B G R B G R B G R B G R B G R B G R B G R B G R ROW79 8380.90 791.00 y coor Pad no. -523.70 329 -470.40 330 -428.60 331 -386.80 332 -345.00 333 -303.20 334 -261.40 335 -219.60 336 -177.80 337 -136.00 338 -94.20 339 -52.40 340 -10.60 341 31.20 342 73.00 343 114.80 344 156.60 345 198.40 346 240.20 347 282.00 348 323.80 349 365.60 350 407.40 351 449.20 352 491.00 353 544.30 354 791.00 355 Name ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ROW64 ROW65 ROW66 ROW67 ROW68 ROW69 ROW70 ROW71 ROW72 x coor 9760.30 9718.50 9676.70 9634.90 9593.10 9551.30 9509.50 9467.70 9425.90 9384.10 9342.30 9300.50 9258.70 9216.90 9175.10 9133.30 9091.50 9049.70 9007.90 8966.10 8924.30 8882.50 8840.70 8798.90 8757.10 8715.30 8673.50 y coor Pad no. 791.00 363 791.00 364 791.00 365 791.00 366 791.00 367 791.00 368 791.00 369 791.00 370 791.00 371 791.00 372 791.00 373 791.00 374 791.00 375 791.00 376 791.00 377 791.00 378 791.00 379 791.00 380 791.00 381 791.00 382 791.00 383 791.00 384 791.00 385 791.00 386 791.00 387 791.00 388 791.00 389 Name COL395 COL394 COL393 COL392 COL391 COL390 COL389 COL388 COL387 COL386 COL385 COL384 COL383 COL382 COL381 COL380 COL379 COL378 COL377 COL376 COL375 COL374 COL373 COL372 COL371 COL370 COL369 Signal SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 Color B G R B G R B G R B G R B G R B G R B G R B G R B G R x coor 8255.50 8213.70 8171.90 8130.10 8088.30 8046.50 8004.70 7962.90 7921.10 7879.30 7837.50 7795.70 7753.90 7712.10 7670.30 7628.50 7586.70 7544.90 7503.10 7461.30 7419.50 7377.70 7335.90 7294.10 7252.30 7210.50 7168.70 y coor 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 7126.90 791.00 7085.10 7043.30 7001.50 6959.70 6917.90 6834.30 6792.50 6750.70 6708.90 6625.30 6583.50 6541.70 6499.90 6458.10 6416.30 6374.50 6332.70 6290.90 6249.10 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 ROW29 10470.90 791.00 6876.10 791.00 ROW34 10261.90 791.00 6667.10 791.00 ROW45 9802.10 6207.30 791.00 6165.50 791.00 Solomon Systech Jul 2005 P 10/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Pad no. 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 Name COL344 COL343 COL342 COL341 COL340 COL339 COL338 COL337 COL336 COL335 COL334 COL333 COL332 COL331 COL330 COL329 COL328 COL327 COL326 COL325 COL324 COL323 COL322 COL321 COL320 COL319 COL318 Signal SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 COL317 www..com B 4995.10 791.00 4953.30 4911.50 4869.70 4827.90 4786.10 4702.50 4660.70 4618.90 4577.10 4493.50 4451.70 4409.90 4368.10 4326.30 4284.50 4242.70 4200.90 4159.10 4117.30 492 COL266 B 2863.30 791.00 2821.50 2779.70 2737.90 2696.10 2654.30 2570.70 2528.90 2487.10 2445.30 2361.70 2319.90 2278.10 2236.30 2194.50 2152.70 2110.90 2069.10 2027.30 1985.50 G R B G R B G R B G R B G R B G R B G R B G R 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 COL265 SEG88 COL264 COL263 COL262 SEG87 COL261 COL260 COL259 SEG86 COL258 COL257 COL256 SEG85 COL255 COL254 COL253 SEG84 COL252 COL251 COL250 SEG83 COL249 COL248 COL247 SEG82 COL246 COL245 COL244 SEG81 COL243 G R B G R B G R B G R B G R B G R B G R B G R 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 4744.30 791.00 2612.50 791.00 Color B G R B G R B G R B G R B G R B G R B G R B G R B G R x coor 6123.70 6081.90 6040.10 5998.30 5956.50 5914.70 5872.90 5831.10 5789.30 5747.50 5705.70 5663.90 5622.10 5580.30 5538.50 5496.70 5454.90 5413.10 5371.30 5329.50 5287.70 5245.90 5204.10 5162.30 5120.50 5078.70 5036.90 y coor Pad no. 791.00 465 791.00 466 791.00 467 791.00 468 791.00 469 791.00 470 791.00 471 791.00 472 791.00 473 791.00 474 791.00 475 791.00 476 791.00 477 791.00 478 791.00 479 791.00 480 791.00 481 791.00 482 791.00 483 791.00 484 791.00 485 791.00 486 791.00 487 791.00 488 791.00 489 791.00 490 791.00 491 Name COL293 COL292 COL291 COL290 COL289 COL288 COL287 COL286 COL285 COL284 COL283 COL282 COL281 COL280 COL279 COL278 COL277 COL276 COL275 COL274 COL273 COL272 COL271 COL270 COL269 COL268 COL267 Signal Color B SEG97 G R B SEG96 G R B SEG95 G R B SEG94 G R B SEG93 G R B SEG92 G R B SEG91 G R B SEG90 G R B SEG89 G R x coor 3991.90 3950.10 3908.30 3866.50 3824.70 3782.90 3741.10 3699.30 3657.50 3615.70 3573.90 3532.10 3490.30 3448.50 3406.70 3364.90 3323.10 3281.30 3239.50 3197.70 3155.90 3114.10 3072.30 3030.50 2988.70 2946.90 2905.10 y coor 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 COL316 SEG105 COL315 COL314 COL313 SEG104 COL312 COL311 COL310 SEG103 COL309 COL308 COL307 SEG102 COL306 COL305 COL304 SEG101 COL303 COL302 COL301 SEG100 COL300 COL299 COL298 SEG99 COL297 COL296 COL295 SEG98 COL294 4535.30 791.00 2403.50 791.00 4075.50 791.00 4033.70 791.00 1943.70 791.00 1901.90 791.00 SSD1783 Series Rev 1.4 P 11/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Pad no. 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 Name COL242 COL241 COL240 COL239 COL238 COL237 COL236 COL235 COL234 COL233 COL232 COL231 COL230 COL229 COL228 COL227 COL226 COL225 COL224 COL223 COL222 COL221 COL220 COL219 COL218 COL217 COL216 Signal Color B SEG80 G R B SEG79 G R B SEG78 G R B SEG77 G R B SEG76 G R B SEG75 G R B SEG74 G R B SEG73 G R B SEG72 G R 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 COL215 COL214 SEG71 COL213 COL212 COL211 SEG70 COL210 COL209 COL208 SEG69 COL207 COL206 COL205 SEG68 COL204 COL203 COL202 SEG67 COL201 COL200 COL199 SEG66 COL198 COL197 COL196 SEG65 COL195 COL194 COL193 SEG64 COL192 www..com B 731.50 791.00 689.70 647.90 606.10 564.30 522.50 438.90 397.10 355.30 313.50 229.90 188.10 146.30 104.50 62.70 20.90 -20.90 -62.70 -104.50 -146.30 594 COL164 B -1400.30 791.00 -1442.10 -1483.90 -1525.70 -1567.50 -1609.30 -1692.90 -1734.70 -1776.50 -1818.30 -1901.90 -1943.70 -1985.50 -2027.30 -2069.10 -2110.90 -2152.70 -2194.50 -2236.30 -2278.10 G R B G R B G R B G R B G R B G R B G R B G R 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 COL163 SEG54 COL162 COL161 COL160 SEG53 COL159 COL158 COL157 SEG52 COL156 COL155 COL154 SEG51 COL153 COL152 COL151 SEG50 COL150 COL149 COL148 SEG49 COL147 COL146 COL145 SEG48 COL144 COL143 COL142 SEG47 COL141 G R B G R B G R B G R B G R B G R B G R B G R 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 480.70 791.00 -1651.10 791.00 x coor 1860.10 1818.30 1776.50 1734.70 1692.90 1651.10 1609.30 1567.50 1525.70 1483.90 1442.10 1400.30 1358.50 1316.70 1274.90 1233.10 1191.30 1149.50 1107.70 1065.90 1024.10 982.30 940.50 898.70 856.90 815.10 773.30 y coor Pad no. 791.00 567 791.00 568 791.00 569 791.00 570 791.00 571 791.00 572 791.00 573 791.00 574 791.00 575 791.00 576 791.00 577 791.00 578 791.00 579 791.00 580 791.00 581 791.00 582 791.00 583 791.00 584 791.00 585 791.00 586 791.00 587 791.00 588 791.00 589 791.00 590 791.00 591 791.00 592 791.00 593 Name COL191 COL190 COL189 COL188 COL187 COL186 COL185 COL184 COL183 COL182 COL181 COL180 COL179 COL178 COL177 COL176 COL175 COL174 COL173 COL172 COL171 COL170 COL169 COL168 COL167 COL166 COL165 Signal Color B SEG63 G R B SEG62 G R B SEG61 G R B SEG60 G R B SEG59 G R B SEG58 G R B SEG57 G R B SEG56 G R B SEG55 G R x coor -271.70 -313.50 -355.30 -397.10 -438.90 -480.70 -522.50 -564.30 -606.10 -647.90 -689.70 -731.50 -773.30 -815.10 -856.90 -898.70 -940.50 -982.30 -1024.10 -1065.90 -1107.70 -1149.50 -1191.30 -1233.10 -1274.90 -1316.70 -1358.50 y coor 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 271.70 791.00 -1860.10 791.00 -188.10 791.00 -229.90 791.00 -2319.90 791.00 -2361.70 791.00 Solomon Systech Jul 2005 P 12/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Pad no. 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 Name COL140 COL139 COL138 COL137 COL136 COL135 COL134 COL133 COL132 COL131 COL130 COL129 COL128 COL127 COL126 COL125 COL124 COL123 COL122 COL121 COL120 COL119 COL118 COL117 COL116 COL115 COL114 Signal Color B SEG46 G R B SEG45 G R B SEG44 G R B SEG43 G R B SEG42 G R B SEG41 G R B SEG40 G R B SEG39 G R B SEG38 G R 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 COL113 COL112 SEG37 COL111 COL110 COL109 SEG36 COL108 COL107 COL106 SEG35 COL105 COL104 COL103 SEG34 COL102 COL101 COL100 SEG33 COL99 COL98 COL97 SEG32 COL96 COL95 COL94 SEG31 COL93 COL92 COL91 SEG30 COL90 www..com B -3532.10 791.00 -3573.90 -3615.70 -3657.50 -3699.30 -3741.10 -3824.70 -3866.50 -3908.30 -3950.10 -4033.70 -4075.50 -4117.30 -4159.10 -4200.90 -4242.70 -4284.50 -4326.30 -4368.10 -4409.90 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 696 G R B G R B G R B G R B G R B G R B G R B G R 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 COL62 COL61 SEG20 COL60 COL59 COL58 SEG19 COL57 COL56 COL55 SEG18 COL54 COL53 COL52 SEG17 COL51 COL50 COL49 SEG16 COL48 COL47 COL46 SEG15 COL45 COL44 COL43 SEG14 COL42 COL41 COL40 SEG13 COL39 B -5663.90 791.00 G R B G R B G R B G R B G R B G R B G R B G R -5705.70 -5747.50 -5789.30 -5831.10 -5872.90 -5956.50 -5998.30 -6040.10 -6081.90 -6165.50 -6207.30 -6249.10 -6290.90 -6332.70 -6374.50 -6416.30 -6458.10 -6499.90 -6541.70 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 -3782.90 791.00 -5914.70 791.00 x coor -2403.50 -2445.30 -2487.10 -2528.90 -2570.70 -2612.50 -2654.30 -2696.10 -2737.90 -2779.70 -2821.50 -2863.30 -2905.10 -2946.90 -2988.70 -3030.50 -3072.30 -3114.10 -3155.90 -3197.70 -3239.50 -3281.30 -3323.10 -3364.90 -3406.70 -3448.50 -3490.30 y coor Pad no. 791.00 669 791.00 670 791.00 671 791.00 672 791.00 673 791.00 674 791.00 675 791.00 676 791.00 677 791.00 678 791.00 679 791.00 680 791.00 681 791.00 682 791.00 683 791.00 684 791.00 685 791.00 686 791.00 687 791.00 688 791.00 689 791.00 690 791.00 691 791.00 692 791.00 693 791.00 694 791.00 695 Name COL89 COL88 COL87 COL86 COL85 COL84 COL83 COL82 COL81 COL80 COL79 COL78 COL77 COL76 COL75 COL74 COL73 COL72 COL71 COL70 COL69 COL68 COL67 COL66 COL65 COL64 COL63 Signal Color B SEG29 G R B SEG28 G R B SEG27 G R B SEG26 G R B SEG25 G R B SEG24 G R B SEG23 G R B SEG22 G R B SEG21 G R x coor -4535.30 -4577.10 -4618.90 -4660.70 -4702.50 -4744.30 -4786.10 -4827.90 -4869.70 -4911.50 -4953.30 -4995.10 -5036.90 -5078.70 -5120.50 -5162.30 -5204.10 -5245.90 -5287.70 -5329.50 -5371.30 -5413.10 -5454.90 -5496.70 -5538.50 -5580.30 -5622.10 y coor 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 -3991.90 791.00 -6123.70 791.00 -4451.70 791.00 -4493.50 791.00 -6583.50 791.00 -6625.30 791.00 SSD1783 Series Rev 1.4 P 13/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Pad no. 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 Name COL38 COL37 COL36 COL35 COL34 COL33 COL32 COL31 COL30 COL29 COL28 COL27 COL26 COL25 COL24 COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16 COL15 COL14 COL13 COL12 Signal Color B SEG12 G R B SEG11 G R B SEG10 G R B SEG9 G R B SEG8 G R B SEG7 G R B SEG6 G R B SEG5 G R B SEG4 G R 747 748 749 750 751 752 753 754 755 756 757 758 COL11 COL10 SEG3 COL9 COL8 COL7 SEG2 COL6 COL5 COL4 COL3 COL2 COL1 COL0 SEG1 www..com B -7795.70 791.00 -7837.50 -7879.30 -7921.10 -7962.90 -8004.70 786 ROW107 -9509.50 791.00 ROW108 ROW109 ROW110 ROW111 ROW112 -9551.30 -9593.10 -9634.90 -9676.70 -9718.50 836 G R B G R B G R B G R 791.00 791.00 791.00 791.00 791.00 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 791.00 791.00 791.00 791.00 791.00 837 838 839 840 841 842 -8046.50 791.00 -8088.30 791.00 -8130.10 791.00 -8171.90 791.00 -8213.70 791.00 -8255.50 791.00 ROW113 -9760.30 791.00 ROW114 -9802.10 791.00 ROW115 -9843.90 791.00 ROW116 -9885.70 791.00 ROW117 -9927.50 791.00 ROW118 -9969.30 791.00 ROW119 ROW120 ROW121 ROW122 ROW123 ROW124 ROW125 ROW126 ROW127 ROW128 -10011.10 -10052.90 -10094.70 -10136.50 -10178.30 -10220.10 -10261.90 -10303.70 -10345.50 -10387.30 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 x coor -6667.10 -6708.90 -6750.70 -6792.50 -6834.30 -6876.10 -6917.90 -6959.70 -7001.50 -7043.30 -7085.10 -7126.90 -7168.70 -7210.50 -7252.30 -7294.10 -7335.90 -7377.70 -7419.50 -7461.30 -7503.10 -7544.90 -7586.70 -7628.50 -7670.30 -7712.10 -7753.90 y coor Pad no. 791.00 759 791.00 760 791.00 761 791.00 762 791.00 763 791.00 764 791.00 765 791.00 766 791.00 767 791.00 768 791.00 769 791.00 770 791.00 771 791.00 772 791.00 773 791.00 774 791.00 775 791.00 776 791.00 777 791.00 778 791.00 779 791.00 780 791.00 781 791.00 782 791.00 783 791.00 784 791.00 785 Name ROW80 ROW81 ROW82 ROW83 ROW84 ROW85 ROW86 ROW87 ROW88 ROW89 ROW90 ROW91 ROW92 ROW93 ROW94 ROW95 ROW96 ROW97 ROW98 ROW99 ROW100 ROW101 ROW102 ROW103 ROW104 ROW105 ROW106 x coor -8380.90 -8422.70 -8464.50 -8506.30 -8548.10 -8589.90 -8631.70 -8673.50 -8715.30 -8757.10 -8798.90 -8840.70 -8882.50 -8924.30 -8966.10 -9007.90 -9049.70 -9091.50 -9133.30 -9175.10 -9216.90 -9258.70 -9300.50 -9342.30 -9384.10 -9425.90 -9467.70 y coor Pad no. 791.00 809 791.00 810 791.00 811 791.00 812 791.00 813 791.00 814 791.00 815 791.00 816 791.00 817 791.00 818 791.00 819 791.00 820 791.00 821 791.00 822 791.00 823 791.00 824 791.00 825 791.00 826 791.00 827 791.00 828 791.00 829 791.00 830 791.00 831 791.00 832 791.00 833 791.00 834 791.00 835 Name ROW130 ROW131 ROW132 ROW133 ROW134 ROW135 DUMMY DUMMY DUMMY ROW136 ROW137 ROW138 ROW139 ROW140 ROW141 ROW142 ROW143 ROW144 ROW145 ROW146 ROW147 ROW148 ROW149 ROW150 ROW151 ROW152 ROW153 x coor -10470.90 -10512.70 -10554.50 -10596.30 -10638.10 -10679.90 -10733.20 -10846.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 y coor 791.00 791.00 791.00 791.00 791.00 791.00 791.00 791.00 544.30 491.00 449.20 407.40 365.60 323.80 282.00 240.20 198.40 156.60 114.80 73.00 31.20 -10.60 -52.40 -94.20 -136.00 -177.80 -219.60 ROW154 -10812.40 -261.40 ROW155 ROW156 ROW157 ROW158 ROW159 -10812.40 -10812.40 -10812.40 -10812.40 -10812.40 -303.20 -345.00 -386.80 -428.60 -470.40 DUMMY -10812.40 -523.70 SEG0 ROW129 -10429.10 791.00 Solomon Systech Jul 2005 P 14/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 6 SSD1783U COF Pin Assignment (Copper View) www..com SSD1783 Series Rev 1.4 P 15/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 7 SSD1783U2 COF Pin Assignment (Copper View) www..com Solomon Systech Jul 2005 P 16/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 8 8.1 PIN DESCRIPTION CS This pin is the chip selection input. The chip is enabled for MCU communication only when CS is pulled low. 8.2 RES This pin is the reset signal input. Initialization of the chip is started once the reset pin is pulled low. The minimum pulse width for reset sequence is 10us. 8.3 D/ C This pin is Data/Command control pin. When the pin is pulled high, the input at D7-D0 is treated as display data. When the pin is pulled low, the input at D7-D0 will be transferred to the command register. 8.4 R / W ( WR ) This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write ( R / W ) selection input. Read mode will be carried out when this pin is pulled high and write mode when this pin is pulled low. When 8080 interface mode is selected, this pin is the Write ( WR ) control signal input. Data write operation is initiated when this pin is pulled low and the chip is selected. 8.5 E ( RD ) This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/ write operation is initiated when this pin is pulled high and the chip is selected. When 8080 interface mode is selected, this pin is the Read ( RD ) control signal input. Data read operation is initiated when this pin is pulled low and the chip is selected. www..com 8.6 PS0 - PS2 These pins are the bus interface mode selection input. Different bus interface can be selected changing the setting of these pins. PS2 H H H L L L PS1 H H L H L L PS0 H L L H H L MPU Interface 16-bit 8080 parallel interface 8-bit 8080 parallel interface 16-bit 6800 parallel interface 8-bit 6800 parallel interface 3-lines serial peripheral interface (SPI) 4-lines serial peripheral interface (SPI) Table 3 - Bus interface mode selection by PS2-PS0 Note1: For serial applications, D0 - D5, D8 - D15, R / W ( WR ), E( RD ) are recommended to connect VDD. Note2: Read back operation is only available in parallel mode 8.7 D0-D15 These pins are the 16-bit bi-directional data bus in parallel interface mode. D15 is the MSB while D0 is the LSB. In serial mode, D7 is the serial data input SDA and D6 is the serial clock input SCK. 8.8 VDD This pin is the system power supply pin of the logic block. SSD1783 Series Rev 1.4 P 17/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 8.9 VDDIO This pin is the system power supply pin of IO buffer. Please refer to Page 71 for connection example. 8.10 VCI This pin is the reference voltage input for internal DC-DC converter. The DC-DC converter output is equal to the multiple factor (4X, 5X, 6X or 7X) times VCI with respect to VSS. Note: Voltage at this input pin must be larger than or equal to VDD. (VCI VDD) 8.11 VCIX2 This pin is a voltage reference output that is equal to 2x VCI. 8.12 VSS This pin is the ground of logic. 8.13 RVSS This pin is the ground of Vref where Vref is the reference voltage of internal regulator. 8.14 CVSS This pin is the ground of analog. 8.15 LCDVSS This pin is the ground of segment and common output pins. www..com 8.16 VOUT This is the most positive voltage supply pin of the chip. It is generated by the internal regulator. This voltage level is used for internal referencing only and the voltage level at VOUT pin is not used for driving external circuitry. 8.17 VOUTD3 This pin is a voltage reference output. 8.18 VL5, VL4, VL3 and VL2 LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship: VOUT > VL5 > VL4 > VL3 > VL2 > VSS 1 : a bias VL5 VL4 VL3 VL2 (a-1)/a * VOUT (a-2)/a * VOUT 2/a * VOUT 1/a * VOUT Table 4 - VOUT > VL5 > VL4 > VL3 > VL2 > VSS Relationship Solomon Systech Jul 2005 P 18/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 8.19 ROW0 - ROW159 These pins provide the driving signals, COMMON, to the LCD panel. 8.20 COL0 - COL395 These pins provide the LCD driving signals, SEGMENT, to the LCD panel. The Red, Green, Blue colors signal are sent out from the SEGMENT output at the same time. The output voltage level of these pins is VDD during sleep mode or standby mode. 8.21 C1P, C1N, C2P, C2N, C1Y, C3P, C4P When internal DC-DC voltage converter is used, external capacitor is connected between these pins. Please refer to the system block diagram for external capacitors connection in Figure 5 on page 25. 8.22 CL This pin is the system clock I/O. This pin is the external clock input for the device, which is enabled by using extended command. It should be left open under normal operation. The internal oscillator will be used after power on reset. 8.23 M This pin is used for cascade purpose only. It should be left open under normal operation. 8.24 SYN This pin is used for cascade purpose only. It should be left open under normal operation. 8.25 BUSY This pin will be high during RAM buffer read/write operation and during graphic commands executing. System programmer should read this pin (low is ready, high is busy) before sending next RAM buffer related command (e.g. RAM write - 5CH; RAM read - 5DH OR any graphic commands) www..com 8.26 NC The No connection (NC) pin should NOT be connected to any signal pin nor shorted to other NC pins in application. It should be left open. 8.27 DUMMY This pin is a floating dummy pin with no internal circuit connection. SSD1783 Series Rev 1.4 P 19/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 9 9.1 FUNCTIONAL BLOCK DESCRIPTIONS Microprocessor Interface Logic The Microprocessor Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-series parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral interface. The selection of different interface is done by PS2, PS1 and PS0 pins. Please refer to the pin descriptions on page 17. a) MPU Parallel 6800-series Interface The parallel Interface consists of 16 bi-directional data pins (D15 - D0), R / W , D/C , E and CS . R / W input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register. R / W input low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E input serves as data latch signal (clock) when high provided that CS is low. Please refer to Figure 16 & Figure 17 for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in the following diagram. GND tcycle E( RD ) DATA BUS www..com n dummy read data read1 n+1 data read 2 n+2 data read 3 N write column address Figure 3 - Read Display Data b) MPU Parallel 8080-series Interface The parallel interface consists of 16 bi-directional data pins D15 - D0, RD , WR , D/ C and CS . RD input serves as data read latch signal (clock) when low provided that CS is low. Whether reading the display data from GDDRAM or reading the status from the status register is controlled by D/ C . WR input serves as data write latch signal (clock) when low provided that CS is low. Whether writing the display data to the GDDRAM or writing the command to the command register is controlled by D/ C . A dummy read is also required before the first actual display data read for 8080-series interface. MPU 4-lines Serial Peripheral Interface The 4-lines serial peripheral Interface consists of serial clock SCK, serial data SDA, D/ C and CS . SDA is shifted into 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6 ...... data bit 0. D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock. Please refer to Figure 20 on page 66 for serial interface timing. c) Solomon Systech Jul 2005 P 20/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com d) MPU 3-lines Serial Peripheral Interface The operation is similar to 4-lines serial peripheral interface while D/ C is not used. There are altogether 9bits will be shifted into the shift register on every ninth clock in sequence: D/ C bit, D7 to D0 bit. The D/ C bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM ( D/ C bit = 1) or the command register ( D/ C bit = 0). 6800 - series Parallel Interface 8080 - series Parallel Interface 16/8-bits 16/8-bits Status only Yes 3-lines or 4-lines Serial peripheral Interface No 8-bits No Yes Data Read Data Write Command Read Command Write 16/8-bits 16/8-bits Status only Yes Table 5 - Data bus selection modes www..com SSD1783 Series Rev 1.4 P 21/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 9.2 Reset Circuit This block is integrated into the Microprocessor Interface Logic which includes Power On Reset circuitry and the hardware reset pin, RES . Both of these having the same reset function. Once the RES pin receives a negative reset pulse, all internal circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 10us. The status of the chip after reset is given by: When RES input is low, the chip is initialized to the following: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Display ON/OFF: Normal/Inverse Display: COM Scan Direction: Internal Oscillator: Reference Voltage Generation Circuit: Voltage regulator and Voltage Follower: Booster: Bias ratio: Multiplex ratio: Contrast level Internal Regulator gain Average temperature gradient: Partial display mode: Start COM address: End COM address: Area Scroll set Top block address: Bottom block address: Number of specified block: Area scroll mode: Scroll start set Start block address: Data Scan Direction Normal/inverse display of page address: Normal/inverse display of column address: Address-scan direction: RGB arrangement: Gray-scale setup: Start Page Address set: End Page Address set: Start Column address set: End Column address set: Select PWM/FRC Display is OFF Normal Display ROW0-ROW159 = COM0-COM159 Disable Disable Disable Disable 1/9 160 Mux 32 7.02 o -0.23%/ C Disable 0 0 0 0 0 Whole screen scroll mode 0 15. 16. www..com Normal Normal Column direction RGB 4K color 0 0 0 0 5-bit PWM + 1-bit FRC mode 17. 18. 19. 20. 21. Solomon Systech Jul 2005 P 22/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 9.3 Command Decoder This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C pin is high, data is written to Graphic Display data RAM (GDDRAM). If it is low, the input at D7 - D0 is interpreted as a Command and it will be decoded. The decoded command will be written to the corresponding command register. 9.4 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 RGB x 168 x 18 = 399168 bits. Figure 4 on page 24 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. Please refer to the command "Data Output/Scan direction" in Table 6 on page 27 for detail description. Four pages of display data form a RAM address block and stored in the GDDRAM. Each block will form the fundamental units of scrolling addresses. Various types of area scrolling can be performed by software program according to the command "Set area Scroll" and "Set Scroll Start" in Table 13 on page 40. www..com SSD1783 Series Rev 1.4 P 23/79 Jul 2005 Solomon Systech www..com www..com 4U www..com no. of bits of data in this cell BLOCK PAGE 0 1 2 0 3 4 5 6 1 7 8 9 10 2 11 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 152 153 154 38 155 156 157 158 159 39 160 161 162 163 164 165 166 167 COL388 SEG129 COL391 SEG130 COL394 SEG131 DATA 66 66 666 66 6 666 666 66 COMMON OUTPUT COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 : : : : : : : : : : : : : : : COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 www..com 40 41 Mapping depends on COM Output scan direction setting SEG0 SEG1 SEGMENT COL0 SEG2 COL387 COL389 COL390 COL392 COL393 COLUMN Notes: Page and SEGMENT data scan direction depend on Data Output Scan Direction Setting. Data Output Scan Direction setting cannot affect the Block scan direction. Figure 4 - Graphic Display Data RAM Map Solomon Systech Jul 2005 P 24/79 COL395 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 9.5 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 4X, 5X, 6X and 7X DC-DC voltage converter. 2. Bias Divider - If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VOUT) to give the LCD driving levels (VL2 - VL5). 3. Contrast Control -Software control of 64 voltage levels of LCD voltage. 4. Bias Ratio Selection circuitry -Software control of 1/7 to 1/14 bias ratio to match the characteristic of LCD panel. 5. Self adjust temperature compensation circuitry - Provide 5 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.23%/C. C4P C6 VCIX2 C2P C2N C1N C1P C3 C2 C1 For 160 mux application, 7x booster configuration, maximum VOUT is 18V. C1 - C4: 1uF C5 - C6: 1uF - 4.7uF C7: 4.7uF C8 - C10: 1uF C11: 0.1uF C7 VOUT C1Y C4 C3P www..com VOUTD3 VL5 VL4 VL3 VL2 C5 C8 C9 C10 C11 Figure 5 - SSD1783 Booster and Divider Configurations SSD1783 Series Rev 1.4 P 25/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 9.6 Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 6). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. Oscillator enable enable Oscillation Circuit enable Buffer (CL) Internal resistor OSC1 OSC2 Figure 6 - Oscillator structural block diagram 9.7 Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. 9.8 HV Buffer Cell (Level Shifter) This block is embedded in the Segment/Common Driver Circuits. HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. The output is shifted out with reference to the internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector, which is synchronized with the internal M signal. www..com 9.9 Level Selector This block is embedded in the Segment/Common Driver circuits. Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. Solomon Systech Jul 2005 P 26/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 10 COMMAND TABLE Table 6 - COMMAND TABLE D/C 0 1 1 0 1 1 0 1 BB 75 Hex 15 D7 0 X7 Y7 0 X7 Y7 1 * D6 0 X6 Y6 1 X6 Y6 0 * D5 0 X5 Y5 1 X5 Y5 1 * D4 1 X4 Y4 1 X4 Y4 1 * D3 0 X3 Y3 0 X3 Y3 1 * D2 1 X2 Y2 1 X2 Y2 0 X2 D1 0 X1 Y1 0 X1 Y1 1 X1 D0 Command 1 X0 Y0 1 X0 Y0 1 X0 Set Page Address Set Column Address Description Set the start column address by X7X6X5X4X3X2X1X0 Set the end column address by Y7Y6Y5Y4Y3Y2Y1Y0 Column address = 00000000b (POR) Column address is in a range of 0~131. Set the start page address by X7X6X5X4X3X2X1X0 Set the end page address by Y7Y6Y5Y4Y3Y2Y1Y0 Page address = 00000000b (POR) Page address is in a range of 0~167. 0 1 1 1 BC 1 * * * 0 * * * 1 * * * 1 * * P34 1 * * P33 1 P12 P22 P32 0 P11 P21 P31 0 P10 P20 P30 Set COM Output X2 X1 X0 ROW0...ROW79 ROW80...ROW159 Scan Direction 0 0 0 COM0 ->COM79 COM80 -> COM159 (POR) 0 0 1 COM0 ->COM79 COM159<-COM80 0 1 0 COM79<-COM0 COM80 -> COM159 0 1 1 COM79<-COM0 COM159<-COM80 Set Data Output a) Normal or Reverse page/column/scan directions Scan Direction P10 = 0: set page address to normal display (POR) P10 = 1: set page address to inverse display P11 = 0: set column address to normal rotation (POR) P11 = 1: set column address to inverse rotation P12 = 0: set scan direction to column scan (POR) P12 = 1: set scan direction to page scan Please refer to the Figure 7 on page 36 for detail description of column/page scan direction modes b) RGB color arrangement P22, P21, P20: The control bits are used for setting the (RGB) color arrangement of segment output. 000 is the POR value. Please refer to the Table 11 on page 37 for detail mapping of the segment output. c) Gray-scale selection P31 P30 Gray-scale modes 00 16-bit/pixel mode 01 8-bit/pixel mode 10 12-bit/pixel mode (POR) 11 18-bit/pixel mode P32 = 0: direct write mode (POR) P32 = 1: use gamma correction P34 P33 0 0 type A (if using 18-bit/pixel mode) (POR) 0 1 type B (if using 18-bit/pixel mode) 1 0 type C (if using 18-bit/pixel mode) Please refer to the Table 12 on page 37 for detail description of different gray-scale selection modes. Different gray-scale selection modes. www..com SSD1783 Series Rev 1.4 P 27/79 Jul 2005 Solomon Systech www..com www..com 4U www..com D/C 0 1 1 Hex CE D7 1 * * D6 1 * * D5 0 X51 X52 D4 0 X41 X42 : : D3 1 X31 X32 D2 1 X21 X22 D1 1 X11 X12 D0 Command 0 X01 X02 Description Set N=32 for 18 bit mode 262K/65K/4K/256 Color Look Up N=32 for 16 bit mode Table (LUT) N=16 for 12 bit mode N=10 for 8 bit mode 1 1 * * * * X58 X59 X48 X49 : : X38 X39 X28 X29 X18 X19 X08 X09 1 1 * * * * X516 X517 X416 X417 : : X316 X317 X216 X217 X116 X117 X016 X017 1 0 1 1 1 CA * 1 0 * 0 * 1 0 * 0 X5N 0 0 Y5 0 X4N 0 0 Y4 0 X3N 1 0 Y3 0 X2N 0 0 Y2 0 X1N 1 0 Y1 0 X0N 0 0 Y0 0 Set Display Control Driver duty selection Select driver duty from 1/32 to 1/160. As Y5 Y4 Y3 Y2 Y1 Y0 is increased from 000111b to 100111b, the number of display lines, N is increased at the same rating. To specify the Y5 Y4 Y3 Y2 Y1 Y0 = (N/4)-1 www..com 0 1 1 1 1 AA 1 * * * * 0 * * * * 1 X5 Y5 Z5 * 0 X4 Y4 Z4 * 1 X3 Y3 Z3 * 0 X2 Y2 Z2 * 1 X1 Y1 Z1 P41 0 X0 Y0 Z0 P40 Set Area Scroll a) Top Block Address X5X4X3X2X1X0 is used to specify the block address (1 block = 4 lines) at the top of the scrolling area. Top block address = 000000b (POR) b) Bottom Block Address Y5Y4Y3Y2Y1Y0 is used to specify the block address (1 block = 4 lines) at the bottom of the scrolling area. Bottom block address = 000000b (POR) c) Number of specified Blocks The number of specified blocks = Number of (Top fixed area + Scroll area) blocks -1. If bottom scroll or whole screen scroll mode is chosen, the number of specified blocks is set to Z5~ Z0 Number of specified blocks = 000000b (POR) d) Area Scroll Mode There are four types of area scroll. Types of Area Scroll P41 P40 0 0 Center Screen Scroll 0 1 Top Screen Scroll 1 0 Bottom Screen Scroll 1 1 Whole Screen Scroll Type of area scroll = Whole Screen Scroll (POR) Solomon Systech Jul 2005 P 28/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com D/C 0 1 0 1 Hex AB D7 1 * D6 0 * 0 * D5 1 X5 1 * D4 0 X4 0 * D3 1 X3 0 X3 D2 0 X2 0 X2 D1 1 X1 0 X1 D0 Command 1 X0 0 X0 Set Scroll Start Description 20 0 * 0 1 1 81 1 * * 0 * * 0 X5 * 0 X4 * 0 X3 * 0 X2 Y2 0 X1 Y1 1 X0 Y0 X5X4X3X2X1X0 specify the start block address (1 block = 4 lines) of area scrolling. Start block address = 000000b (POR) Set Power Control X0=0: turns off the reference voltage generator (POR) Register X0=1: turns on the reference voltage generator X1=0: turns off the internal regulator and voltage follower (POR) X1=1: turns on the internal regulator and voltage follower Select booster level X3 X2 Boost level 00 4X 01 5X 10 6X 11 7X Set Contrast Level & a) Select contrast level from 64 contrast steps Internal Regulator Contrast increases as X5X4X3X2X1X0 is increased Resistor Ratio from 000000b to 111111b. X5X4X3X2X1X0 = 100000b (POR) b) The internal regulator gain (1+R2/R1) VOUT increases as Y2Y1Y0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: Y2Y1Y0 = 000: 7.02 (POR) Y2Y1Y0 = 001: 7.89 Y2Y1Y0 = 010: 8.76 Y2Y1Y0 = 011: 9.63 Y2Y1Y0 = 100: 10.5 Y2Y1Y0 = 101: 11.37 Y2Y1Y0 = 110: 12.24 Y2Y1Y0 = 111: 13.11 X0=0: The contrast set of voltage regulator is incremented by 1 X0=1: The contrast set of voltage regulator is decremented by 1 X0=0: normal display (POR) X0=1: inverse display www..com 0 D6 - D7 1 1 0 1 0 1 1 X0 Increment / Decrement of the contrast set Set Normal/Inverse Display 0 0 1 1 0 0 0 0 A9 AE - AF 94 - 95 D1 - D3 A6 - A7 A8 1 1 X7 Y7 1 1 1 1 0 0 X6 Y6 0 0 0 1 1 1 X5 Y5 1 1 0 0 0 0 X4 Y4 0 0 1 1 0 1 X3 Y3 1 1 0 0 1 0 X2 Y2 0 1 1 0 1 0 X1 Y1 0 1 0 X1 X0 0 X0 Y0 1 X0 X0 X0 Enter partial Display X7X6X5X4X3X2X1X0 : Start COM Address = 0000000b (POR) Y7Y6Y5Y4Y3Y2Y1Y0 : End COM Address = 0000000b (POR) Exit partial Display Set Display On/Off Enter/Exit sleep mode Enable/disable internal oscillator Exit the "partial display mode" by executing the command 10101001b (POR) X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel X0=0: exit the sleep mode. X0=1: enter sleep mode. (POR) X1 X0 01 10 Internal oscillator status ON OFF (POR) SSD1783 Series Rev 1.4 P 29/79 Jul 2005 Solomon Systech www..com www..com 4U www..com D/C 0 1 Hex 82 D7 1 * D6 0 * D5 0 * D4 0 * D3 0 * D2 0 * D1 1 X1 D0 Command 0 X0 Set temperature compensation coefficient Description Average temperature gradients X1 X0 Average Temperature Gradient [%/oC] 00 -0.10 01 -0.15 10 -0.23(POR) 11 -0.30 The average temperature gradient will be set to -0.03%/oC. This command will overwrite the command from 0X82. 0 1 1 1 1 0 F4 08 00 58 03 25 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 Set the smallest temperature compensation coefficient NOP Command result in No Operation The command should be issued after the execution of the Status Read command 0 1 5C 0 Y71 1 Y61 0 Y51 1 Y41 1 Y31 1 Y21 0 Y11 0 Y01 www..com Remark: "*" denote DON'T CARE bit Write display data Enter the "write display data mode " by executing the command 01011100b. The following byte is used to specify the data byte to be written to the GDDRAM directly. The D/C bit should be stated at logic "1" during the display data is written to the GDDRAM. Solomon Systech Jul 2005 P 30/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 7 - Graphic command table D/C 0 1 1 1 1 1 1 1 1 0 1 92 Hex 83 D7 D6 D5 D4 1 A7 B7 C7 D7 R4 G2 R3 * 1 * 0 A6 B6 C6 D6 R3 G1 R2 * 0 A6 0 A5 B5 C5 D5 R2 G0 R1 * 0 A5 0 A4 B4 C4 D4 R1 B4 R0 * 1 A4 D3 0 A3 B3 C3 D3 R0 B3 G3 B3 0 A3 D2 0 A2 B2 C2 D2 G5 B2 G2 B2 0 A2 D1 1 A1 B1 C1 D1 G4 B1 G1 B1 1 A1 D0 Command 1 A0 B0 C0 D0 G3 B0 G0 B0 0 A0 Fill Enable/Disable Draw Line Description Enter the "Draw line mode" by executing the command 10000011. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The remaining two bytes are used to specify the color. 16-bits color will be used for 18/16-bit pixel mode, 12 bit color will be used for 12/8-bit pixel mode. For 16-bit color For 12-bit color Remark: A, C 131, A < C; B, D 159, B < D Enter the "Fill Enable/Disable mode" by executing the command 10010010. A0=0: Filled color option is disabled (POR) A0=1: Filled color option is enabled A3A2=00: no gradient fill (POR) A3A2=01: enable x-direction gradient fill A3A2=10: enable y-direction gradient fill A3A2=11: enable x and y direction gradient fill www..com A6=0: dim to white (POR) A6=1: dim to black 0 1 1 1 1 1 1 1 1 1 1 1 1 84 1 A7 B7 C7 D7 R4 G2 R4 G2 R3 * R3 * 0 A6 B6 C6 D6 R3 G1 R3 G1 R2 * R2 * 0 A5 B5 C5 D5 R2 G0 R2 G0 R1 * R1 * 0 A4 B4 C4 D4 R1 B4 R1 B4 R0 * R0 * 0 A3 B3 C3 D3 R0 B3 R0 B3 G3 B3 G3 B3 1 A2 B2 C2 D2 G5 B2 G5 B2 G2 B2 G2 B2 0 A1 B1 C1 D1 G4 B1 G4 B1 G1 B1 G1 B1 0 A0 B0 C0 D0 G3 B0 G3 B0 G0 B0 G0 B0 Draw rectangle A5A4=00: set gradient slope to pixel distance /1 (largest) (POR) A5A4=01: set gradient slope to pixel distance /2 A5A4=10: set gradient slope to pixel distance /4 A5A4=11: set gradient slope to pixel distance /8 (smallest) For 16-bit color Enter the "Draw rectangle mode" by executing the command 10000100. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The next two bytes are used to specify the border color. The last two bytes are used to specify the fill color. (depends on fill option of command 0x92). If gradient fill is enabled in command 0x92, the data byte which specific the border color is also used to specify the x,y coordinate of gradient start, and it should be within the rectangle. For 12-bit color Remark: A, C 131, A < C; B, D 159, B < D SSD1783 Series Rev 1.4 P 31/79 Jul 2005 Solomon Systech www..com www..com 4U www..com D/C 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 Hex 86 D7 D6 D5 D4 1 A7 B7 C7 R4 G2 R4 G2 R3 * R3 * 0 A6 B6 C6 R3 G1 R3 G1 R2 * R2 * 0 A6 B6 C6 D6 F6 0 A6 B6 C6 0 A5 B5 C5 R2 G0 R2 G0 R1 * R1 * 0 A5 B5 C5 D5 F5 0 A5 B5 C5 0 A4 B4 C4 R1 B4 R1 B4 R0 * R0 * 0 A4 B4 C4 D4 E4 F4 0 A4 B4 C4 D3 0 A3 B3 C3 R0 B3 R0 B3 G3 B3 G3 B3 1 A3 B3 C3 D3 E3 F3 1 A3 B3 C3 D2 1 A2 B2 C2 G5 B2 G5 B2 G2 B2 G2 B2 0 A2 B2 C2 D2 E2 F2 1 A2 B2 C2 D1 1 A1 B1 C1 G4 B1 G4 B1 G1 B1 G1 B1 1 A1 B1 C1 D1 F1 0 A1 B1 C1 E1 D0 Command 0 A0 B0 C0 G3 B0 G3 B0 G0 B0 G0 B0 0 A0 B0 C0 D0 F0 0 A0 B0 C0 Dim Window E0 Copy Draw circle Description Enter the "Draw circle mode" by executing the command 10000110. The first three bytes (A0 to A7, B0 to B7, C0 to C7) are used to specify the centre's X coordinate, Y coordinate, circle's radius respectively. The next two bytes are used to specify the border color. The last two bytes are used to specify the fill color (depends on fill option of command 0x92). For 16-bit color For 12-bit color Remark: 0 A7~A0 255; 0 B7~B0 255; 1 C7~C0 255 Enter the "Copy mode" by executing the command. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The remaining two bytes (E0 to E7, F0 to F7) are used to specify the new location of X coordinates and Y coordinates. Remarks: A, C 131, A < C; B, D 159, B < D Enter the "Dim Window mode" by executing the command 10001100. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The selected window area will be dimmed by 75% white or black according to data bit A6 of command 0x92 Remarks: A, C 131, A < C; B, D 159, B < D Enter the "Clear Window mode" by executing the command 10001110. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. All pixels contrast will be set to 0. Remarks: A, C 131, A < C; B, D 159, B < D 8A 1 A7 B7 C7 D7 E7 F7 E6 E5 www..com 8C 1 A7 B7 C7 1 0 1 1 1 1 8E D7 1 A7 B7 C7 D7 D6 0 A6 B6 C6 D6 D5 0 A5 B5 C5 D5 D4 0 A4 B4 C4 D4 D3 1 A3 B3 C3 D3 D2 1 A2 B2 C2 D2 D1 1 A1 B1 C1 D1 D0 0 A0 B0 C0 D0 Clear Window Remark: "*" denote DON'T CARE bit After executed the graphic command, waiting time is required for update GDDRAM content. (When VDD=2.4~3.0V, waiting time = 340ns/pixel; When VDD=3.0~3.6V, waiting time = 270ns/pixel) Solomon Systech Jul 2005 P 32/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 8 - Extended command table D/C 0 1 Hex FB D7 D6 1 * 1 * D5 1 * D4 1 * D3 1 0 D2 0 B2 D1 1 B1 D0 Command 1 Set biasing ratio B0 Description Allow user to set bias from 1/ 7 to 1/14 B2B1B0 000 001 010 011 100 101 110 111 0 1 1 F2 1 0 0 1 0 N6 1 0 N5 1 0 N4 0 F3 N3 0 F2 N2 1 F1 N1 0 F0 N0 Set Frame frequency and N-line Inversion Bias ratio 1/7 bias 1/8 bias 1/9 bias (POR) 1/10 bias 1/11 bias 1/12 bias 1/13 bias 1/14 bias This command uses to change the frame frequency; set the N-line inversion and N-line inversion mode F3F2F1F0 1 1 1 1 : 103 Hz 1 1 1 0 : 99 Hz 1 1 0 1 : 95 Hz 1 1 0 0 : 91 Hz 1 0 1 1 : 87 Hz www..com 1 0 1 0 : 83 Hz 1 0 0 1 : 79 Hz 1 0 0 0 : 75 Hz (POR) 0 1 1 1 : 71 Hz 0 1 1 0 : 67 Hz 0 1 0 1 : 63 Hz 0 1 0 0 : 59 Hz 0 0 1 1 : 55 Hz 0 0 1 0 : 51 Hz 0 0 0 1 : 47 Hz 0 0 0 0 : 43 Hz The second byte data N5N4N3N2N1N0 sets the n-line inversion register from 2 to 64 lines to reduce display crosstalk. Register values from 000001b to 111111b are mapped to 2 lines to 64 lines respectively. Value 00000b disables the N-line inversion. 010000 is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of mux should NOT be a multiple of the lines of inversion (n). N6 0 - reset n-line counter per frame (POR) 1 - will not reset n-line counter per frame SSD1783 Series Rev 1.4 P 33/79 Jul 2005 Solomon Systech www..com www..com 4U www..com D/C 0 0 1 1 1 0 1 1 1 Hex A2 - A3 F7 28 05 F1 D7 D6 1 1 0 X7 0 1 1 0 0 0 1 0 0 0 1 1 0 0 D5 1 1 1 0 0 1 X1 0 0 D4 0 1 0 0 0 1 X0 0 0 D3 0 0 1 1 0 0 0 0 0 D2 0 1 0 1 1 0 0 0 0 D1 1 1 0 1 0 0 0 0 0 D0 Command X0 Reserved 1 0 X0 1 1 0 0 0 Set COM sequence Select PWM/FRC Description X7 0 0 0 1 1 1 X0 0 0 0 0 1 1 1 0 : 5 bits PWM + 1 bit FRC (POR) 0 0 0 0 1 1 1 1 : 6 bits FRC 1 0 0 0 1 1 1 0 : 4 bits PWM + 2 bits FRC 1 0 0 0 1 1 1 1 : Reserved X1 X0 0 0 1 1 0: 1: 0: 1: COM0 - 79 COM80 - 159 0 0 COM0 - COM79 COM80 - COM159 (POR) COM0 - COM31, COM32 - COM63, COM64 - COM111 COM112 - COM159 COM1 - COM159 (odd) COM0 - COM158 (even) COM0 - COM158 (even) COM1 - COM159 (odd) 0 1 1 F6 0A 1 0 0 1 0 0 1 0 0 1 1 0 0 X3 1 1 X2 0 1 X1 1 0 X0 0 OTP setting This command set the offset value of contrast X3X2X1X0 0111 : original contrast + 7 step 0110 : original contrast + 6 step 0101 : original contrast + 5 steps 0100 : original contrast + 4 steps 0011 : original contrast + 3 steps 0010 : original contrast + 2 steps 0001 : original contrast + 1 steps 0000 : original contrast (POR) 1111 : original contrast - 1 steps 1110 : original contrast - 2 steps 1101 : original contrast - 3 steps 1100 : original contrast - 4 steps 1011 : original contrast - 5 steps 1010 : original contrast - 6 steps 1001 : original contrast - 7 steps 1000 : original contrast - 8 step www..com 0 F8 1 1 1 1 1 0 0 0 OTP programming This command starts to program LCD driver with OTP offset value. Each bit can be programmed to 1 once. Detail of OTP programming procedure on page 45 Solomon Systech Jul 2005 P 34/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 9 - Read Command Table D/C 0 1 Hex 5D D7 0 Y71 D6 1 Y61 D5 0 Y51 D4 1 Y41 D3 1 Y31 D2 1 Y21 D1 0 Y11 D0 Command 1 Y01 Read display data Description Enter the "read display data mode " by executing the command 01011101b. The next byte is a dummy data. The GDDRAM data will be read form the second byte. The GDDRAM column address pointer will be increased by one automatically after each 2-bytes data read. (64K color mode). D7D6 = 00: Center Screen Scroll Mode D7D6 = 01: Top Screen Scroll Mode D7D6 = 10: Bottom Screen Scroll Mode D7D6 = 11: Whole Screen Scroll Mode D4 = 0: Scan Direction is column direction D4 = 1: Scan Direction is page direction D3 = 0: Display is OFF D3 = 1: Display is ON 0 0 5D 0 1 0 1 1 1 0 1 Status Register Read D7 D6 D5 D4 D3 D2 D1 D0 www..com D2 = 0: Sleep Mode is disabled D2 = 1: Sleep Mode is enabled D1 = 0: Display is Inverse D1 = 1: Display is Normal D0 = 0: Partial display is disabled D0 = 1: Partial display is enabled Note: Command patterns other than that given in Command Table are prohibited. Otherwise, unexpected result will occur. Remark: "*" denote DON'T CARE bit SSD1783 Series Rev 1.4 P 35/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 10.1 Data Read / Write To read data from the GDDRAM, 5DH command should be executed then input High to R / W ( WR ) pin and D/C pin for 6800-series parallel mode. Low to E( RD ) pin and High to D/C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read in 8-levels gray scale mode OR after each 3-bytes data read in 16-levels gray scale mode. Also, a dummy read is required before the first data is read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R / W ( WR ) pin and High to D/ C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write in 8-levels gray scale mode OR each 3-bytes data write in 16-levels scale mode. The address will be reset to 0 in next data read/write operation is executed when it is 103. www..com Solomon Systech Jul 2005 P 36/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 11 COMMAND DESCRIPTIONS 11.1 Set Column Address (15 H) This command specifies the 8-bit column address of the display data RAM. The start and the end column address are specified by this command. The driver supports up to 132 columns. As the addresses are incremented from the start column to the end column in the column direction scan, the page address is incremented by 1. The column address is then returned to the start column. The column address will be increased by each data access after it is preset by the MCU. Start column < End column must be maintained. RGB Alignment using 262K color mode Column 0 1 B1 R2 G2 B2 R1 G1 B1 R2 G2 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2 D15 D14 D13 D12 D11 D10 P11=0 Color R1 Data D15 D14 D13 D12 D11 D10 G1 D7 D6 D5 D4 D3 D2 B2 D7 D6 D5 D4 D3 D2 R1 D15 D14 D13 D12 D11 D10 G1 D7 D6 D5 D4 D3 D2 B1 65 R2 D7 D6 D5 D4 D3 D2 G2 D15 D14 D13 D12 D11 D10 B2 D7 D6 D5 D4 D3 D2 P11=1 Color BLOCK 0 Page P10=0 0 1 2 3 4 5 6 7 : : : : : : : : : 156 157 158 159 160 161 162 163 164 165 166 167 www..com : : : : : : : : : 1 : : : : : : : : : 39 40 41 R2 Data D7 D6 D5 D4 D3 P10=1 D2 167 166 165 164 163 162 161 160 : : : : : : : : : 11 10 9 8 7 6 5 4 3 2 1 0 G2 D15 D14 D13 D12 D11 D10 B2 D7 D6 D5 D4 D3 D2 65 R1 D15 D14 D13 D12 D11 D10 G1 D7 D6 D5 D4 D3 D2 B1 D15 D14 D13 D12 D11 D10 R2 D7 D6 D5 D4 D3 D2 G2 D15 D14 D13 D12 D11 D10 B2 D7 D6 D5 D4 D3 D2 64 R1 D15 D14 D13 D12 D11 D10 G1 D7 D6 D5 D4 D3 D2 B1 D15 D14 D13 D12 D11 D10 R2 D7 D6 D5 D4 D3 D2 COL390 COL391 COL392 COL393 COL394 SEGMENT OUTPUTS Table 10 - RAM arrangements of 18-bit/pixel, direct write mode. SSD1783 Series Rev 1.4 P 37/79 Jul 2005 Solomon Systech COL395 COL10 COL11 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 } } G2 D15 D14 D13 D12 D11 D10 B2 D7 D6 D5 D4 D3 D2 0 R1 D15 D14 D13 D12 D11 D10 G1 D7 D6 D5 D4 D3 D2 B1 D15 D14 D13 D12 D11 D10 LCD Read Direction Page D15 D14 D13 D12 D11 D10 } } www..com www..com 4U www..com 11.2 Set Page Address (75 H) This command enters the page address from 0 to 167 to the RAM page register for read/write operations. The driver supports up to 160 lines. All in all, there are 168 pages. As the addresses are incremented from the start page to the end page in the page direction scan, the column address is incremented by 1. The page address is then returned to the start page. Start page < End page must be maintained. 11.3 Set COM Output Scan Direction (BB H) This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. Please refer to the Table 6 on Page 27 for detail mapping. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect. 11.4 Set Data Output Scan Direction (BC H) This command sets the DDRAM such that the MPU operates the display data in the internal RAM. A. Normal or Inverse page/column/scan directions The Data Scan direction can be set to either normal or inverse display page and column address scan direction. The column and the page direction are illustrated in the following figure. P12 = 0: Column Direction P11=0 0 1 P11=1 131 130 P10=0 P10=1 0 159 1 158 2 157 : : : : : : 157 2 158 1 159 0 P12 = 1: Page Direction P11=0 0 P11=1 131 P10=0 P10=1 0 159 1 158 2 157 : : : : : : 157 2 158 1 159 0 2 129 129 2 130 1 131 0 www..com 1 130 2 129 129 2 130 1 131 0 : : : : : : Figure 7 - column and page scan direction Solomon Systech Jul 2005 P 38/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com The parameters following the command set data output scan direction specifies the RGB arrangement and the selection of various gray-scale modes. Please find the information of the RGB arrangement and the gray scale mode in the following section. B. RGB arrangement mode The RGB arrangement mode can be selected according to the following table. Three selection bits will give eight combinations of the RGB arrangements. Each combination set will specify the Red, Green and Blue segment output arrangement in odd and even page. P22, P21, P20 000 (POR) 001 010 011 100 101 110 111 LINE Even page Odd page 1 2 1 2 1 2 1 2 1 2 1 2 1 2 COL0 R R B B R R B B R B B R R B B R COL1 G G G G G G G G G G G G G G G G COL2 B B R R B B R R B R R B B R R B COL3 R R B B B B R R R B B R B R R B COL4 G G G G G G G G G G G G G G G G COL5 B B R R R R B B B R R B R B B R COL6 R R B B R R B B R B B R R B B R COL7 G G G G G G G G G G G G G G G G ... ... ... ... ... ... ... ... ... COL395 B B R R R R B B B R R B R B B R Table 11 - RGB Arrangement modes C. Gray scale mode Gray scale selection and corresponding data bus arrangement for different bus interface mode are illustrated in the following table. Bus interface mode (select by PS2PS0, ref to Table 3 ) 16 bit 8 bit 8 bit 16 bit 8 bit Data bus arrangement (D15......D0) for 16 bit bus mode, (D7......D0) for 8 bit bus mode ( "*" denote don't care bit ) RRRRRGGGGGGBBBBB RRRRRGGG (byte 1) GGGBBBBB (byte 2) RRRGGGBB RRRRGGGGBBBB**** RRRRGGGG (byte 1) BBBBRRRR (byte 2) GGGGBBBB (byte 3) RRRRRR**GGGGGG** (word 1) BBBBBB**RRRRRR** (word 2) GGGGGG**BBBBBB** (word 3) RRRRRR**GGGGGG** (word 1) ********BBBBBB** (word 2) RRRRRR**GGGGGG** (word 1) BBBBBB********** (word 2) RRRRRR** (byte 1) GGGGGG** (byte 2) BBBBBB** (byte 3) www..com P34, P33 P31, P30 Gray Scale selection Note 00 01 10 16-bit / pixel 8-bit / pixel 12-bit / pixel ** ** ** 1 word / 1 pixel 2 byte/ 1 pixel 1 byte / 1 pixel 1 word / 1 pixel 3 byte / 2 pixel 3 word / 2 pixel 2 word / 1 pixel 2 word / 1 pixel 3 byte / 1 pixel 00 16 bit 11 18-bit / pixel 11 8 bit ** 01 Table 12 - Data bus arrangement for different pixel and bus mode SSD1783 Series Rev 1.4 P 39/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 11.5 Set Color Look Up Table (CE H) This command is used to set the color look up table (LUT) for different pixel mode. The LUT has 32 6-bit entries, the number of entry to write depends on different pixel mode, the 6 LSB of each of the data byte following this command correspond to one entry of the LUT. Pixel mode 18 or 16 bit/pixel 12 bit/pixel 8 bit/pixel No. of entry 32 16 10 Note 32 data byte (6 LSB of each) define the LUT 16 data byte (6 LSB of each) define the LUT 10 data byte (6 LSB of each) define the LUT with st 1 8 byte define all 8 colors of Red and Green, while st th Blue will use 1 and 8 byte for data 00, 11 th th correspondingly, and will use 9 and 10 byte for data 01 and 10 correspondingly. 11.6 Set Display Control (CA H) This command is used to select the duty ratio of the IC. All available driving duty can be selected using this command. The driving duty can be changed from 1/32 to 1/160 11.7 Set Area Scroll (AA H) This command specifies the portion of screen for scrolling. The command sets the starting block address, finishing block address, number of specific blocks and the area scroll mode of the area scrolling. Please be noted that the starting block address should be smaller than the finishing block address. th The block address increment direction is started at 0 block such that the GDDRAM address corresponds to the top of the fixed area. Similarly, the block address decrement direction is started at the 41st block such that the GDDRAM address corresponds to the bottom fixed area. The remaining block address excluding the top and the bottom fixed areas are assigned to the scroll plus the background areas. The set area scroll function is divided into four parts. www..com th Part I -Specify the top block address of the scroll + the background areas. Specify the 0 block for the top screen scroll or the whole screen scroll. The scroll start block address is also set at this top block address until the scroll start set command is executed. Part II - Specify the bottom address of the scroll + background areas. Specify the 41 block for the bottom or the whole screen scroll. Part III - Specify number of scrolled blocks = number of (Top fixed area + scroll area) blocks -1. When the bottom scroll or whole screen scroll is chosen, the resulted value is identical to the value stated in part II. Part IV st Specify the area scroll type. Altogether there are four types of area scroll. Please refer to Table 13 for detail. P41 0 0 1 1 P40 0 1 0 1 Types of Area Scroll Center Screen Scroll Top Screen Scroll Bottom Screen Scroll Whole Screen Scroll Table 13 - Area scrolling selection modes Solomon Systech Jul 2005 P 40/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Center Screen Top Screen Bottom Screen Whole Screen Scroll : Fixed Area : Scroll Area Figure 8 - Area scrolling selection modes The area scroll function is executed by prompt in the set area scroll command following by changing the start block address by the set scroll start command. Figure 8 illustrates the operation model of the scrolling function. www..com SSD1783 Series Rev 1.4 P 41/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Example: In the Center screen scroll of 1/128 duty (display range: 128 lines = 32 blocks) Description Command Set Area Scroll AA H 8 lines (block 0 and block 1) is specified for the top fixed area Top block address = Number of lines in top fixed area / 4 = 8/4 =2 8 lines (block 40 & block 41) are specified for the bottom fixed area Bottom block address = 41 - (number of lines in bottom fixed area / 4) = 41 - (8 / 4) = 41 - 2 = 39 112 lines (block 2 to block 29) are specified the scroll area Number of specified block = Top block address + (number of lines in scroll area/4) - 1 = 2 + (112 / 4) -1 = 2 + 28 - 1 = 29 40 lines (block 30 to block 39) are specified the background areas Set area scroll mode - Center screen mode Set Scroll start (Scroll range form 02H ~ 0DH) ABH Data 02 H 27 H 1D H 00 H 02 H DDRAM: LCD panel 0 1 2 www..com 29 30 32 blocks = 128 line 39 40 41 Fixed area Display area Scroll area Background area Figure 9 - GDDRAM updates for area scrolling Solomon Systech Jul 2005 P 42/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Block 132 RGB X 168 Line GDDRAM Content Top Fix Area 0 : 3 4 : : : : : 27 28 : : 37 38 : 41 0 : 3 4 : : Scroll Start : : =4 : : 27 38 : 41 0 : 3 8 : : Scroll Start: =8 : : : 31 38 : 41 132 RGB X 128 lines Panel COM0 Scroll Area Background Area Bottom Fix Area COM127 COM0 Example Program of Specified Center Scroll mode. Void center_scroll(void) { //Set 128 Mux Comm_out (0xCA); COM127 COM0 0 : 3 Data_out (0x1F); 12 Data_out(0x00); Scroll Start: //Set Area Scroll = 12 : Comm_out(0xAA); : Data_out(0x04); // Top Block Address : Data_out(0x25); // Specified Bottom Block Address : Data_out(0x1B); //Number of Specified Block : Data_out(0x00); //Center Screen Mode 35 //Set Scroll Start 38 for (I=0x04; I<=0x37; I++) : { 41 Comm_out(0xAB); //set scroll start Data_out(I); 0 Delay (200); //delay 200ms : } 3 } 20 : : Scroll Start: = 20 : : 9 Data_out (0x00); www..com COM127 COM0 38 : 41 Figure 10 - Example of center scroll mode COM127 SSD1783 Series Rev 1.4 P 43/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 11.8 Set Scroll Start (AB H) This command specifies the starting block address of the area scrolling and then executes the area scroll by changing the start block address dynamically. Start block < End block must be maintained. Please be noted that the set scroll start command should be executed after the set area scroll command. 11.9 Set Power Control Register (20 H) This command turns on/off the various power circuits associated with the chip. There are three power sub-circuits (reference voltage generator, internal regulator and voltage follower) could be turned on/off by this command. In addition, the configuration of the internal primary booster (4X/5X/6X/7X) can be selected by this command. 11.10 Set Contrast Level and Internal Regulator Resistor Ratio (IR) (81 H) This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, VOUT, provided by the OnChip power circuits. VOUT is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. Please refer to the Figure 11 for the contrast control process flow diagram. Set Contrast Control Register Contrast Level Data No Changes Complete? Yes Figure 11 - Contrast Control Flow Set Segment Re-map This command also sets the feedback gain of the internal regulator. There are altogether 8 internal regulator gains, which are used for the adjustment of VOUT level. This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network. The Contrast Control Voltage Range curves is referred to the following formula: www..com R Vout = 1 + 2 *Vcon R 1 63 - Vcon = 1 - * Vref 210 , where Vref = 1.7V Solomon Systech Jul 2005 P 44/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Contrast Control Voltage Range 25 23 21 19 17 15 13 11 9 7 5 0 4 8 48 36 40 44 52 56 12 16 20 24 28 32 60 IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 Vop (V) Contrast Figure 12 - Contrast Control Voltage Range Curve 11.11 Set Increment/Decrement of the contrast set (D6/D7 H) This command can increase the contrast step by +1 (D6 H) and decrease the contrast step by -1 (D7 H). It is the most convenient way to change the contrast of the display by programming. www..com 11.12 Set Normal/Inverse Display (A6/A7 H) This command turns the display to be either normal (A6 H) or inverse (A7). In normal display mode, a RAM data of 1 indicates an illumination on the corresponding pixel in the normal white panel. In inverse display mode, a RAM data of 0 will turn on the pixel. It should be noted that the icon line is not affected. The icon line is not inversed by this command. Example: For a normal white display panel (Set Normal Display: A6Hex): RAM Content Color R G B 0 0 0 White F F F Black 0 F F Red F 0 F Green F F 0 Blue SSD1783 Series Rev 1.4 P 45/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 11.13 Enter Partial Display (A8 H) This command and the following parameters specify the display area of the partial display mode. The following figure shows the display and non-display area when the partial display mode is executed. : Display area (Partial Display Area) : Non-display area Figure 13 - Partial display mode 11.14 Exit Partial Display (A9 H) This command exits the partial display mode. 11.15 Set Display On/Off (AF/AE H) This command is used to turn the display on (AF H) or off (AE H). When display off is issued with entire display is on, power save mode will be entered. 11.16 Enter/Exit sleep mode (95/94 H) This command enter (95 H) or exit (94 H) the sleep mode. www..com 11.17 Enable/Disable the internal oscillator (D1/D2 H) This command enables (D1 H) or disables (D2 H) the internal oscillator. The internal oscillator is turned off after reset. 11.18 Set Temperature compensation coefficient (82 H) This command sets the average temperature gradients. Four sets of average temperature gradients can be selected. Please refer to the command table for detail description of the average temperature gradients. The default value of 0 the temperature gradient is -0.20 %/ C 11.19 NOP (25 H) A command causing the chip takes No Operation. 11.20 Write display data mode (5C H) This command is used to execute the write display data mode. The display data byte is directly written to the GDDRAM. Please be noted that the D/ C signal should be set to high during the display data is written to the GDDRAM. 11.21 Read display data mode (5D H) This command is used to execute the read display data mode. The display data byte is directly read from the GDDRAM. Please be noted that the D/ C signal should be set to high during the display data is red from to the GDDRAM. Solomon Systech Jul 2005 P 46/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 11.22 Set biasing ratio (FB H) This command selects a suitable bias ratio (1/7 to 1/14) required for driving the particular LCD panel in use. 11.23 Set Frame Frequency (F2 H) This command specifies the frame frequency so as to minimize the flickering due to the ac main frequency. The frequency is set to 75 Hz after POR. 11.24 Set N-line inversion (F2 H) Number of line inversion is set by this command for reducing crosstalk noise. 2 to 64-line inversion operations could be selected. At POR, this operation is set to 10000b (17 lines). It should be noted that the total number of mux should NOT be a multiple of the inversion number (n). Or else, some lines will not change their polarity during frame change. The n-line counter can be set such that it will be reset per display frame (POR). 11.25 Select PWM/FRC (F7 H) This command set the Pulse Width Modulation, Frame Rate Control or mix of FWM & FRC. 11.26 OTP setting (F6 H) OTP (One Time Programming) is a method to adjust VOUT. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules. Each OTP bit can be programmed to `1' one time. OTP setting and programming should include two major steps. Find the OTP offset and OTP programming as following, www..com SSD1783 Series Rev 1.4 P 47/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Step 1. Find OTP offset (1) (2) (3) (4) Hardware Reset (sending an active low reset pulse to RES pin) Send original initialization routines Set and display any test patterns Adjust the contrast value (C:0x81, D:0x00~0x3F, D: 0x00 ~ 0x07) until there is the best visual contrast (5) OTP setting steps = Contrast value of the best visual contrast - Contrast value of original initialization Example 1: Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x24 OTP offset value = 0x24 - 0x20 = +4 OTP setting command should be (C: 0xF6, D: 0x14, D: 0x0A) Example 2: Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x1B OTP setting = 0x1B - 0x20 = -5 OTP setting command should be (C:0xF6, D: 0x1B, D: 0x0A) Step 2. OTP programming (6) Hardware Reset (sending an active low reset pulse to RES pin) (7) Enable Oscillator (C: 0xD1) and Exit Sleep Mode (C: 0x94) (8) Connect an external VOUT by closing SW1 (see diagram below) (9) Send OTP setting commands that we find in step 1 (C: 0xF6, D: 0x10~0x1F, D: 0x0A) (10)Send OTP programming command (C: 0xF8) (11)Wait at least 2 seconds (12)Hardware Reset (13)Disconnect the external Vout by opening SW1 (14)Discharge the capacitor C by closing the switch SW2 and wait for 1 second (15)Hardware Reset (16)Verify the result by repeating step 1. (2) - (3) www..com SSD1783 SW1 (8) C + GND VOUT R1 R2 14.5-15.5V GND GND SW2 (13) (1) & (6) & (14) RES Note: R1 = 1K ~ 2k ohm R2 = 100 ohm C = 1u ~ 4.7u F Figure 14 - OTP programming circuitry Solomon Systech Jul 2005 P 48/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Start Step 2 Step 1 i) Hardware reset ii) Send original initialization routines iii) Set and display any test patterns i) Hardware reset ii) Enable oscillator Adjust the contrast level to the best visual level Connect an external voltage (14.5~15.5V) on VOUT pins Accept the contrast level on panel? No www..com Yes OTP setting steps = Adjusted contrast value - Original contrast value i) Send original initialization routines ii) Set and display any test patterns iii) Inspect the contrast i) Send OTP setting commands ii) Send OTP programming command iii) Wait > 2 sec vi) Disconnect the external Vout v) Discharge the Vout's capacitor iv) Hardware reset END Figure 15 - Flow chart of OTP programming Procedure SSD1783 Series Rev 1.4 P 49/79 Jul 2005 Solomon Systech www..com www..com 4U www..com OTP Example program Find the OTP offset: 1. 2. Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XD1); COMMAND(0X94); 3. 4. COMMAND(0X20); DATA(0x0F); COMMAND(0XFB) DATA(0X2) 5. COMMAND(0X81) DATA(0X14) DATA(0X05) 6. \\Enable oscillator; \\ exit sleep mode; \\ turn on the reference voltage generator, internal regulator and voltage follower; Select booster level. \\ Set Biasing ratio \\ 1/9 \\Set target gain and contrast. \\ contrast = 20 \\ Internal Regulator Gain = 11.37 \\ Set target display contents COMMAND(0X15) DATA(0x00) DATA(0X83) COMMAND(0X75) DATA(0X00) DATA(0X9F) COMMAND(0X5C) DATA(...) COMMAND(0xAF) \\ set column address \\ set start column address at 0 \\ set end column address at 131 \\ set page address \\ set start page address at 0 \\ set end page address at 159 \\ write target content to GDDRAM 7. 8. 9. 10. 11. 12. OTP offset calculation... target OTP offset value is +3 www..com \\ display on \\ Enable Oscillator \\ Exit Sleep Mode OTP programming: Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XD1) COMMAND(0x94) Connect a external VOUT (14.5V~15.5V) COMMAND(0XF6) DATA(0X13) DATA(0x0A) \\ Set OTP offset value to +3 (0011) \\ 0001 X3X2X1X0 , where X3X2X1X0 is the OTP offset value 13. 14. 15. 16. 17. COMMAND(0XF8) \\ Send the OTP programming command. Wait at least 2 seconds for programming wait time. Disconnect an external Vout Discharge the Vout's capacitor Hardware reset by sending an active low reset pulse to RES pin Verify the result: 18. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel. Solomon Systech Jul 2005 P 50/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 11.27 Draw Line (83 H) Given the starting point (X1, Y1) and the ending point (X2, Y2), a line will be drawn with the color specified. The following example illustrates the line drawing procedure. 1. Enter the "draw line mode" by execute the command 83H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 01H 5. Set the finishing Y-coordinates, Y2. E.g., 01H 6. Set the color to RGB = (0,1,0) e.g., 07H followed by E0H Result: A green line will be drawn between coordinates (0,0) and (1,1) Remark: X1, X2 131; X1 < X2 Y1, Y2 159; Y1 < Y2 11.28 Fill Enable/Disable (92 H) This command allows the fill color option to be enabled or disabled. This command is applicable to the Draw Rectangle feature. When the selection bit is "0", the fill color option is disabled. When the selection bit is "1", the fill color option is enabled. 11.29 Draw rectangle (84 H) Given the starting point (X1, Y1) and the ending point (X2, Y2), specify the width and height of a rectangle that will be drawn with the color specified. Remarks: If fill color option is disabled, the enclosed area will not be filled. www..com The following example illustrates the rectangle drawing procedure. 1. Enter the "draw rectangle mode" by execute the command 8AH 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 02H 5. Set the finishing Y-coordinates, Y2. E.g., 02H 6. Set the color to RGB = (1,0,0) e.g., F8H following by 00H 7. Set the filled color to RGB = (0,1,0) e.g., 07H following by E0H Result: A rectangle will be drawn at (0,0) to (2,2), filled green with red border Remark: X1, X2 131; X1 < X2 Y1, Y2 159; Y1 < Y2 SSD1783 Series Rev 1.4 P 51/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 11.30 Draw Circle (86 H) Given the center point (X1, Y1) and the radius R, a circle will be drawn with the color specified. Remarks: If fill color option is disabled, the enclosed area will not be filled. color R X1, Y1 fill color The following example illustrates the rectangle drawing procedure. 1. Enter the "draw circle mode" by execute the command 86H 2. Set the center X-coordinates, X1. E.g., 40H. 3. Set the center Y-coordinates, Y1. E.g., 40H. 4. Set the radius, R. E.g., 20H 5. Set the color to RGB = (1,0,0) e.g., F8H following by 00H 6. Set the filled color to RGB = (0,1,0) e.g., 07H following by E0H Result: A circle will be drawn with center (64,64) and radius 32, filled green with red border Remark: 0 X1,Y1 255 1 R 255 www..com Solomon Systech Jul 2005 P 52/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 11.31 Copy (8A H) Copy the rectangular region defined by the starting point (X1, Y1) and the ending point (X2, Y2) to location (X3, Y3). There are two possible results with the command copy executed depending on the setting of the start point coordinates and end point coordinates. The following example illustrates the copy procedure. Case 1 - The overlap region will superimpose. 1. Enter the "copy mode" by execute the command 84H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 02H 5. Set the finishing Y-coordinates, Y2. E.g., 02H 6. Set the New X-coordinates, X3. E.g., 01H 7. Set the New Y-coordinates, Y3. E.g., 01H Case 2 - The original content remains unchanged www..com 1. Enter the "copy mode" by execute the command 84H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 01H 5. Set the finishing Y-coordinates, Y2. E.g., 01H 6. Set the New X-coordinates, X3. E.g., 09H 7. Set the New Y-coordinates, Y3. E.g., 09H Remark: X1, X2 131; X1 < X2 Y1, Y2 159; Y1 < Y2 SSD1783 Series Rev 1.4 P 53/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 11.32 Dim Window (8C H) This command will dim the window area specify by starting point (X1, Y1) and the ending point (X2, Y2). After the execution of this command, the selected window area will be dimmed by 75% white. Additional execution of this command over the same window area will not change the data content. Remark: X1, X2 131; X1 < X2 Y1, Y2 159; Y1 < Y2 11.33 Clear Window (8E H) This command sets the window area specify by starting point (X1, Y1) and the ending point (X2, Y2) to clear the window display. The GDDRAM content of the window will be set to zero. Remark: X1, X2 131; X1 < X2 Y1, Y2 159; Y1 < Y2 11.34 Status register read The following parameters can be monitored by the status read register. 1. Various area scroll mode 2. Read modify mode ON/OFF 3. Column scan direction 4. Page scan direction 5. Display ON/OFF 6. Sleep mode ON/OFF 7. Display Normal/Inverse 8. Partial display mode ON/OFF www..com Solomon Systech Jul 2005 P 54/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 12 MAXIMUM RATINGS Table 14 - Maximum Ratings (Voltage Referenced to VSS) Symbol VDD VOUT VCI I TA Tstg Parameter Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Value -0.3 to +4.0 -0.3 to 18 VSS-0.3 to 4.0 25 -40 to +85 -65 to +150 Unit V V V mA o o C C Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VCI and Vout be constrained to the range VSS < VDD VCI < VOUT. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. www..com SSD1783 Series Rev 1.4 P 55/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 13 DC CHARACTERISTICS Table 15 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.6V, TA = -40 to 85C) Symbol VDD VDDIO VCI Parameter System power supply pins of the logic block Range Test Condition Recommend Operating Voltage Possible Operating Voltage Recommend Operating Voltage Power supply pin of IO pins Possible Operating Voltage Booster Reference Supply Recommend Operating Voltage Voltage Range (3) Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 7X DC-DC , 16-bit 8080 parallel bus Access Mode Supply Current writing AAAA HTcyc =3MHz, Typ. Drain (VDD Pins) Osc. Freq., Display On, no panel attached. VDD = 2.7V, VOUT = 16V, Voltage Generator On, 7X DC-DC Display Mode Supply Current Converter Enabled, R/W(WR) Halt, Drain (VDD Pins) Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, LCD Driving Waveform Sleep Mode Supply Current Off, Oscillator Off, R/W(WR) halt. Drain (VDD Pins) Display On, Voltage Generator Enabled, DC-DC Converter LCD Driving Voltage Generator Enabled, Typ. Osc. Freq., Output (VOUT Pin) Regulator Enabled, Divider Enabled. Logic High Output Voltage Logic Low Output Voltage Logic High Input voltage Logic Low Input voltage Logic High Output Current VOUT = VDD-0.4V Source Logic Low Output Current Drain VOUT = 0.4V Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Regulator Enabled, Internal Variation of VOUT Output (VDD is Contrast Control Enabled, Set fixed) Contrast Control Register = 0 IOUT=-100A IOUT=100A Min 2.4 1.2 VDD Typ 2.7 VDD VDD Max 3.6 VDD 3.6 Unit V V V IAC - 650 950 A IDP2 - 500 800 A ISLEEP - 2 5 A VOUT 8 0.9* VDD 0 0.8* VDD 0 50 -1 -1 -2 0 -0.12 -0.19 -0.26 - 18 V VOH1 VOL1 VIH1 VIL1 IOH IOL IOZ IIL/IIH CIN VOUT RO www..com 5 0 500 -0.10 -0.15 -0.23 -0.30 VDD 0.1*VD D V V V V A A A A pF % ohm %/ C %/ C %/ C %/ C o o o o VDD 0.2* VDD -50 1 1 7.5 2 -0.12 -0.19 -0.26 -0.34 SEG/COM output resistance Average Temperature Gradient TC0 Flat Temperature Coefficient TC1 Temperature Coefficient 1* Voltage Regulator Enabled Temperature Coefficient 2* TC2 (POR) TC3 Temperature Coefficient 3* *The formula for the temperature coefficient is: o o 1 x 100 % TC(%) = Vref at 50 C - Vref at 0 C x o o o 50 C - 0 C Vref at 25 C Solomon Systech Jul 2005 P 56/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 14 AC CHARACTERISTICS Table 16 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.7V, TA = 25 C) Symbol Fosc Parameter Oscillation Frequency of Display Timing Generator for: 160 MUX Mode Frame Frequency for: 160 MUX Mode Test Condition Min Internal Oscillator Enabled (default), 374 VDD = 2.7V 132 RGB x 160 Graphic Display Mode, Display ON, Internal Oscillator Enabled 73 Typ Max 394 Unit kHz o 380 75 FFRM 77 Hz Remarks: Fosc stands for the frequency value of internal oscillator www..com SSD1783 Series Rev 1.4 P 57/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Table 17 - Parallel Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.3V) Symbol tcycle PW H PW L tR tF CSW H tAS tAH tDSW tDHW tACC tOH Parameter Clock Cycle Time (write cycle) Minimum Pulse Width High Minimum Pulse Width Low Rise Time Fall Time CS Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time Min 130 55 55 50 15 10 10 20 15 20 Typ Max 10 10 200 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns D/C tAS R/W tAH tcycle CS www..com tF CSW H PW H PW L tDHW tDSW Valid Data tACC tR E D0~D15(WRITE) D0~D7(READ) Valid Data tOH Figure 16 - 8-bit/16-bit Parallel 6800-series Interface Timing Characteristics Solomon Systech Jul 2005 P 58/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 18 - Parallel Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.3V) Symbol tcycle PW L PW H tR tF CSW H tAS tAH tDSW tDHW tACC tOH Write Cycle (Case 1) D/C tAS tAH Parameter Clock Cycle Time (write cycle) Minimum Pulse Low Minimum Pulse High Rise Time Fall Time CS Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time Min 130 55 55 50 15 10 10 20 15 20 Typ - Max 10 10 - 170 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns CS tcycle PW L PW H CSW H WR tF tR RD www..com tDSW tDHW Valid Data D0~D15(WRITE) Write Cycle (Case 2) D/C tAS tAH WR tcycle PW H CSW H CS PW L tF tR RD tDSW tDHW D0~D15(WRITE) Valid Data SSD1783 Series Rev 1.4 P 59/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Write Cycle (Case 3) D/C tAS tAH WR tcycle PW H CS PW L tF tR RD tDSW tDHW D0~D15(WRITE) Valid Data Write Cycle (Case 4) D/C tAS tAH CS www..com tcycle PW L PW H WR tF tR RD tDSW tDHW D0~D15(WRITE) Valid Data Solomon Systech Jul 2005 P 60/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Read Cycle (Case 1) D/C tAS tAH tR tcycle CS tF WR PW H PW L RD tACC D0~D7(READ) Valid Data tOH Read Cycle (Case 2) D/C www..com tAS tAH RD tF tR GND t WR PW H PW L CS tACC D0~D7(READ) Valid Data tOH Figure 17 - 8-bit/16-bit Parallel 8080-series Interface Timing Characteristics SSD1783 Series Rev 1.4 P 61/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Table 19 - Parallel Timing Characteristics (TA = -40 to 85C, VDD = 2.4V) Symbol tcycle PW H PW L tR tF CSW H tAS tAH tDSW tDHW tACC tOH Parameter Clock Cycle Time (write cycle) Minimum Pulse Width High Minimum Pulse Width Low Rise Time Fall Time CS Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time Min 250 125 125 100 15 10 10 20 15 20 Typ Max 10 10 170 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns D/C tAS R/W tAH tcycle CS tF PW H tR CSW H PW L E www..com tDSW tDHW Valid Data tACC D0~D15(WRITE) D0~D7(READ) Valid Data tOH Figure 18 - 8-bit/16-bit Parallel 6800-series Interface Timing Characteristics Solomon Systech Jul 2005 P 62/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 20 - Parallel Timing Characteristics (TA = -40 to 85C, VDD = 2.4V) Symbol tcycle PW L PW H tR tF CSW H tAS tAH tDSW tDHW tACC tOH Parameter Clock Cycle Time (write cycle) Minimum Pulse Low Minimum Pulse High Rise Time Fall Time CS Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time Min 250 125 125 100 15 10 10 20 15 20 Typ Max 10 10 170 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle (Case 1) D/C tAS tAH CS tcycle PW L PW H CSW H WR www..com tF tDSW tDHW Valid Data tR RD D0~D15(WRITE) Write Cycle (Case 2) D/C tAS tAH WR tcycle PW H CSW H CS PW L tF tR RD tDSW tDHW D0~D15(WRITE) Valid Data SSD1783 Series Rev 1.4 P 63/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Write Cycle (Case 3) D/C tAS tAH WR PW L tcycle PW H CS tF tR RD tDSW tDHW D0~D15(WRITE) Valid Data Write Cycle (Case 4) D/C CS www..com tAS tcycle PW L PW H tAH WR RD tF tR tDSW tDHW D0~D15(WRITE) Valid Data Solomon Systech Jul 2005 P 64/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Read Cycle (Case 1) tAS tAH tR CS tF WR PW L RD tACC D0~D7(READ) Valid Data Read Cycle (Case 2) D/C www..com tAH RD tF tR GND t WR PW L CS D0~D7(READ) Figure 19 - 8-bit/16-bit Parallel 8080-series Interface Timing Characteristics SSD1783 Series Rev 1.4 P 65/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Table 21 - Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V) Symbol tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Min 66 90 20 10 30 10 10 15 15 Typ Max 15 Unit ns MHz ns ns ns ns ns ns ns ns D/C tAS tAH tCSH tcycle CS tCSS tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) www..com Valid Data CS SCK(D6) SDA(D7) D7 D6 D5 D4 D3 D2 D1 D0 Figure 20 - 4 wire Serial Timing Characteristics (PS2=PS1=PS0=L) Solomon Systech Jul 2005 P 66/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 22 - Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V) Symbol tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Min 66 90 20 10 30 10 10 15 15 Typ Max 15 Unit ns MHz ns ns ns ns ns ns ns ns CS tCSS tcycle tCSH tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) www..com Valid Data CS SCK(D6) SDA(D7) D/C D7 D6 D5 D4 D3 D2 D1 D0 Figure 21 - 3 wire Serial Timing Characteristics (PS2=PS1=L, PS0=H) SSD1783 Series Rev 1.4 P 67/79 Jul 2005 Solomon Systech www..com www..com 4U www..com Table 23 - Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.4V) Symbol tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Min 100 90 20 10 30 10 10 15 15 Typ Max 10 Unit ns MHz ns ns ns ns ns ns ns ns D/C tAS tAH tCSH tcycle CS tCSS tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) www..com Valid Data CS SCK(D6) SDA(D7) D7 D6 D5 D4 D3 D2 D1 D0 Figure 22 - 4 wire Serial Timing Characteristics (PS2=PS1=PS0=L) Solomon Systech Jul 2005 P 68/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com Table 24 - Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.4V) Symbol tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH Parameter Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Min 100 90 20 10 30 10 10 15 15 Typ Max 10 Unit ns MHz ns ns ns ns ns ns ns ns CS tCSS tcycle tCSH tCLKL tCLKH SCK(D6) tF tDSW tR tDHW SDA(D7) www..com Valid Data CS SCK(D6) SDA(D7) D/C D7 D6 D5 D4 D3 D2 D1 D0 Figure 23 - 3 wire Serial Timing Characteristics (PS2=PS1=L, PS0=H) SSD1783 Series Rev 1.4 P 69/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 15 APPLICATION EXAMPLES COM0 : : : : : COM79 160 X 132 RGB PANEL command for output scan direction D/ C =0 BB H D/ C =1 01 H COM80 : : : : : COM159 SEG0 ROW82 ROW81 ROW80 COL0 : : : : : : : : : : COL383 COL384 : : COL395 SEG395 ROW79 ROW64 ROW63 ROW2 ROW1 ROW0 ROW158 ROW159 SSD1783 VOUTD3 LCDVSS VDDIO www..com VDD VSS VSS VSS C1P C1Y C3P VL2 VL3 VL4 C11 VCI C9 C8 C6 C7 2.775V C5 VCIX2 VOUT RVSS CVSS C2N C1N C4P C2P C13 C14 C12 C4 C3 C2 C1 C1,C2 C3 C4 C5 C6,C7 C8* C9 C11,C12 C13,C14 value 1uF (25V) 1uF (10V) 0.1uF (6V) 1uF (10V) 1uF (6V) 4.7uF (25V) 1uF (16V) 1uF (25V) 1uF (25V) size* 0805 0805 0805 0805 0805 1210 0805 0805 0805 VDD = VDDIO = VCI = 2.775V PS2='H', PS1=PS0='L' (16 bit 6800 bus) *For C8, part of it could be put on PCB to make the total cap value ~4.7uF if cap size is too big to place on COF *the size is for reference only Figure 24 - Application example Solomon Systech Jul 2005 P 70/79 Rev 1.4 VL5 SSD1783 Series www..com www..com 4U www..com 2.7V VDD RES, PS2, PS1, PS0, D/C, WR, E, CS, D0-D15 VSS VDDIO VDD VDD MCU SSD1783 VSS a) VDD= VDDIO= VCI= VDD(MCU) =2.7V 1.8V 2.7V www..com VDD RES, PS2, PS1, PS0, D/C, WR, E, CS, D0-D15 VDDIO VDD VDD MCU VSS SSD1783 VSS b) VDD= VCI=2.7V, VDDIO= VDD(MCU)=1.8V Figure 25 - VDD, VDDIO, VCI connections for (a) typical voltage MCU and (b) low voltage MCU SSD1783 Series Rev 1.4 P 71/79 Jul 2005 Solomon Systech www..com www..com 4U www..com 16 SSD1783Z DIE TRAY DIMENSIONS www..com Spec W1 W2 X1 Px Py X Y Z N mm (mil) (2992) (2677) (158) (1185) (132) (878) (85) (24) Figure 26 - SSD1783Z Die Tray Dimension 76.0 +0..2 -0 1 68.0 +0..2 -0 1 4.0 0.1 30.10 0.1 3.34 0.1 22.30 0.1 2.16 0.1 0.61 0.05 38 Solomon Systech Jul 2005 P 72/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com 17 APPENDIX SSD1783U Drawing 1 www..com SSD1783 Series Rev 1.4 P 73/79 Jul 2005 Solomon Systech www..com www..com 4U www..com SSD1783U Drawing 2 www..com Solomon Systech Jul 2005 P 74/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com SSD1783U Drawing 3 www..com SSD1783 Series Rev 1.4 P 75/79 Jul 2005 Solomon Systech www..com www..com 4U www..com SSD1783U2 Drawing 1 www..com Solomon Systech Jul 2005 P 76/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com SSD1783U2 Drawing 2 www..com SSD1783 Series Rev 1.4 P 77/79 Jul 2005 Solomon Systech www..com www..com 4U www..com SSD1783U2 Drawing 3 www..com Solomon Systech Jul 2005 P 78/79 Rev 1.4 SSD1783 Series www..com www..com 4U www..com www..com Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part http://www.solomon-systech.com SSD1783 Series Rev 1.4 P 79/79 Jul 2005 Solomon Systech www..com www..com 4U |
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